DE60100829D1 - Stromschalterlogikschaltung zur Erzeugung gleicher Anstiegs- und Abfallzeiten - Google Patents

Stromschalterlogikschaltung zur Erzeugung gleicher Anstiegs- und Abfallzeiten

Info

Publication number
DE60100829D1
DE60100829D1 DE60100829T DE60100829T DE60100829D1 DE 60100829 D1 DE60100829 D1 DE 60100829D1 DE 60100829 T DE60100829 T DE 60100829T DE 60100829 T DE60100829 T DE 60100829T DE 60100829 D1 DE60100829 D1 DE 60100829D1
Authority
DE
Germany
Prior art keywords
power switch
logic circuit
fall times
switch logic
generate equal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60100829T
Other languages
English (en)
Other versions
DE60100829T2 (de
Inventor
Hiroaki Asano
Mitsuru Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE60100829D1 publication Critical patent/DE60100829D1/de
Publication of DE60100829T2 publication Critical patent/DE60100829T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE60100829T 2000-07-07 2001-07-04 Stromschalterlogikschaltung zur Erzeugung gleicher Anstiegs- und Abfallzeiten Expired - Fee Related DE60100829T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000207176A JP2002026719A (ja) 2000-07-07 2000-07-07 完全差動型論理回路
JP2000207176 2000-07-07

Publications (2)

Publication Number Publication Date
DE60100829D1 true DE60100829D1 (de) 2003-10-30
DE60100829T2 DE60100829T2 (de) 2004-07-01

Family

ID=18703982

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60100829T Expired - Fee Related DE60100829T2 (de) 2000-07-07 2001-07-04 Stromschalterlogikschaltung zur Erzeugung gleicher Anstiegs- und Abfallzeiten

Country Status (4)

Country Link
US (1) US6911847B2 (de)
EP (2) EP1320194A1 (de)
JP (1) JP2002026719A (de)
DE (1) DE60100829T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7867858B2 (en) * 2008-03-31 2011-01-11 Freescale Semiconductor, Inc. Hybrid transistor based power gating switch circuit and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414314A (ja) * 1990-05-08 1992-01-20 Toshiba Corp ソース電極結合形論理回路
US5777505A (en) * 1996-01-25 1998-07-07 The Boeing Company Low-power crosspoint switch

Also Published As

Publication number Publication date
US6911847B2 (en) 2005-06-28
JP2002026719A (ja) 2002-01-25
EP1320194A1 (de) 2003-06-18
US20020003439A1 (en) 2002-01-10
EP1170867B1 (de) 2003-09-24
EP1170867A1 (de) 2002-01-09
DE60100829T2 (de) 2004-07-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8339 Ceased/non-payment of the annual fee