DE60045093D1 - Speicher und befehle in einer rechnerarchitektur mit prozessor und coprozessor - Google Patents

Speicher und befehle in einer rechnerarchitektur mit prozessor und coprozessor

Info

Publication number
DE60045093D1
DE60045093D1 DE60045093T DE60045093T DE60045093D1 DE 60045093 D1 DE60045093 D1 DE 60045093D1 DE 60045093 T DE60045093 T DE 60045093T DE 60045093 T DE60045093 T DE 60045093T DE 60045093 D1 DE60045093 D1 DE 60045093D1
Authority
DE
Germany
Prior art keywords
coprocessor
commands
processor
memory
computer architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60045093T
Other languages
English (en)
Inventor
Andrea Olgiati
Dominic Paul Mccarthy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE60045093D1 publication Critical patent/DE60045093D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE60045093T 1999-06-15 2000-06-15 Speicher und befehle in einer rechnerarchitektur mit prozessor und coprozessor Expired - Lifetime DE60045093D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99304659A EP1061439A1 (de) 1999-06-15 1999-06-15 Speicher und Befehlen in Rechnerarchitektur mit Prozessor und Coprozessor
PCT/GB2000/002331 WO2000077627A1 (en) 1999-06-15 2000-06-15 Memory and instructions in computer architecture containing processor and coprocessor

Publications (1)

Publication Number Publication Date
DE60045093D1 true DE60045093D1 (de) 2010-11-25

Family

ID=8241459

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60045093T Expired - Lifetime DE60045093D1 (de) 1999-06-15 2000-06-15 Speicher und befehle in einer rechnerarchitektur mit prozessor und coprozessor

Country Status (5)

Country Link
US (1) US6782445B1 (de)
EP (2) EP1061439A1 (de)
JP (1) JP5283810B2 (de)
DE (1) DE60045093D1 (de)
WO (1) WO2000077627A1 (de)

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
ATE243390T1 (de) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen umladen von datenflussprozessoren (dfps) sowie bausteinen mit zwei- oder mehrdimensionalen programmierbaren zellstrukturen (fpgas, dpgas, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
WO2002013000A2 (de) 2000-06-13 2002-02-14 Pact Informationstechnologie Gmbh Pipeline ct-protokolle und -kommunikation
DE10081643D2 (de) 1999-06-10 2002-05-29 Pact Inf Tech Gmbh Sequenz-Partitionierung auf Zellstrukturen
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
WO2005045692A2 (en) 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7155602B2 (en) 2001-04-30 2006-12-26 Src Computers, Inc. Interface for integrating reconfigurable processors into a general purpose computing system
US7210022B2 (en) * 2001-05-15 2007-04-24 Cloudshield Technologies, Inc. Apparatus and method for interconnecting a processor to co-processors using a shared memory as the communication interface
EP1402382B1 (de) * 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
WO2003050723A1 (en) * 2001-12-05 2003-06-19 Src Computers, Inc. An interface for integrating reconfigurable processors into a general purpose computing system
WO2003052586A2 (en) * 2001-12-14 2003-06-26 Koninklijke Philips Electronics N.V. Data processing system having multiple processors
EP1483682A2 (de) 2002-01-19 2004-12-08 PACT XPP Technologies AG Reconfigurierbarer prozessor
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
DE10221206B4 (de) * 2002-05-13 2008-04-03 Systemonic Ag Burst Zugriffsverfahren auf Co-Prozessoren
US20040006667A1 (en) * 2002-06-21 2004-01-08 Bik Aart J.C. Apparatus and method for implementing adjacent, non-unit stride memory access patterns utilizing SIMD instructions
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
WO2004042562A2 (en) * 2002-10-31 2004-05-21 Lockheed Martin Corporation Pipeline accelerator and related system and method
US7386704B2 (en) 2002-10-31 2008-06-10 Lockheed Martin Corporation Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method
US7430652B2 (en) * 2003-03-28 2008-09-30 Tarari, Inc. Devices for performing multiple independent hardware acceleration operations and methods for performing same
US20050055594A1 (en) * 2003-09-05 2005-03-10 Doering Andreas C. Method and device for synchronizing a processor and a coprocessor
JP2005202767A (ja) * 2004-01-16 2005-07-28 Toshiba Corp プロセッサシステム、dma制御回路、dma制御方法、dmaコントローラの制御方法、画像処理方法および画像処理回路
US7743376B2 (en) * 2004-09-13 2010-06-22 Broadcom Corporation Method and apparatus for managing tasks in a multiprocessor system
US20060101250A1 (en) 2004-10-01 2006-05-11 Lockheed Martin Corporation Configurable computing machine and related systems and methods
US7472261B2 (en) * 2005-11-08 2008-12-30 International Business Machines Corporation Method for performing externally assisted calls in a heterogeneous processing complex
JP2009524134A (ja) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト ハードウェア定義方法
US8032734B2 (en) * 2006-09-06 2011-10-04 Mips Technologies, Inc. Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
US9946547B2 (en) 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US7934063B2 (en) 2007-03-29 2011-04-26 International Business Machines Corporation Invoking externally assisted calls from an isolated environment
US8144702B1 (en) * 2007-06-14 2012-03-27 Xilinx, Inc. Generation of a pipeline for processing a type of network packets
US7817657B1 (en) 2007-06-14 2010-10-19 Xilinx, Inc. Circuit for processing network packets
US7788470B1 (en) * 2008-03-27 2010-08-31 Xilinx, Inc. Shadow pipeline in an auxiliary processor unit controller
US9152427B2 (en) 2008-10-15 2015-10-06 Hyperion Core, Inc. Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file
US9104403B2 (en) * 2010-08-18 2015-08-11 Freescale Semiconductor, Inc. Data processing system having selective redundancy and method therefor
JP2012252374A (ja) 2011-05-31 2012-12-20 Renesas Electronics Corp 情報処理装置
US9880852B2 (en) * 2012-12-27 2018-01-30 Intel Corporation Programmable hardware accelerators in CPU
US10929059B2 (en) 2016-07-26 2021-02-23 MemRay Corporation Resistance switching memory-based accelerator
US10936198B2 (en) 2016-07-26 2021-03-02 MemRay Corporation Resistance switching memory-based coprocessor and computing device including the same
JP2018120448A (ja) * 2017-01-26 2018-08-02 ソニーセミコンダクタソリューションズ株式会社 演算処理装置および情報処理システム
US11294678B2 (en) 2018-05-29 2022-04-05 Advanced Micro Devices, Inc. Scheduler queue assignment
US11138009B2 (en) * 2018-08-10 2021-10-05 Nvidia Corporation Robust, efficient multiprocessor-coprocessor interface
US11334384B2 (en) * 2019-12-10 2022-05-17 Advanced Micro Devices, Inc. Scheduler queue assignment burst mode
US11249766B1 (en) 2020-09-14 2022-02-15 Apple Inc. Coprocessor synchronizing instruction suppression
US11948000B2 (en) 2020-10-27 2024-04-02 Advanced Micro Devices, Inc. Gang scheduling for low-latency task synchronization
US20220374368A1 (en) * 2021-05-19 2022-11-24 Hughes Network Systems, Llc System and method for enhancing throughput during data transfer
CN116804915B (zh) * 2023-08-28 2023-12-15 腾讯科技(深圳)有限公司 基于存储器的数据交互方法、处理器、设备以及介质

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4099236A (en) * 1977-05-20 1978-07-04 Intel Corporation Slave microprocessor for operation with a master microprocessor and a direct memory access controller
JPS5840214B2 (ja) * 1979-06-26 1983-09-03 株式会社東芝 計算機システム
US4589067A (en) * 1983-05-27 1986-05-13 Analogic Corporation Full floating point vector processor with dynamically configurable multifunction pipelined ALU
US6438683B1 (en) * 1992-07-28 2002-08-20 Eastman Kodak Company Technique using FIFO memory for booting a programmable microprocessor from a host computer
US5708830A (en) * 1992-09-15 1998-01-13 Morphometrix Inc. Asynchronous data coprocessor utilizing systolic array processors and an auxiliary microprocessor interacting therewith
US5884050A (en) * 1996-06-21 1999-03-16 Digital Equipment Corporation Mechanism for high bandwidth DMA transfers in a PCI environment
US5784582A (en) * 1996-10-28 1998-07-21 3Com Corporation Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline
EP0862118B1 (de) 1997-01-09 2004-02-04 Hewlett-Packard Company, A Delaware Corporation Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung
EP0853283A1 (de) * 1997-01-09 1998-07-15 Hewlett-Packard Company Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung
DE69727465T2 (de) 1997-01-09 2004-12-23 Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung
EP0858167A1 (de) 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Prozessor
EP0858168A1 (de) 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Gatterprozessor
EP0924625B1 (de) 1997-12-17 2004-11-17 Elixent Limited Konfigurierbare Verarbeitungsanordnung und Verfahren zur Benutzung dieser Anordnung um eine Zentraleinheit aufzubauen
DE69827589T2 (de) 1997-12-17 2005-11-03 Elixent Ltd. Konfigurierbare Verarbeitungsanordnung und Verfahren zur Benutzung dieser Anordnung, um eine Zentraleinheit aufzubauen
US6442671B1 (en) * 1999-03-03 2002-08-27 Philips Semiconductors System for priming a latch between two memories and transferring data via the latch in successive clock cycle thereafter

Also Published As

Publication number Publication date
JP2003502728A (ja) 2003-01-21
WO2000077627A1 (en) 2000-12-21
EP1061439A1 (de) 2000-12-20
EP1104562B1 (de) 2010-10-13
US6782445B1 (en) 2004-08-24
EP1104562A1 (de) 2001-06-06
JP5283810B2 (ja) 2013-09-04

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, US