DE60041300D1 - Sequentielle Bus-Architektur - Google Patents

Sequentielle Bus-Architektur

Info

Publication number
DE60041300D1
DE60041300D1 DE60041300T DE60041300T DE60041300D1 DE 60041300 D1 DE60041300 D1 DE 60041300D1 DE 60041300 T DE60041300 T DE 60041300T DE 60041300 T DE60041300 T DE 60041300T DE 60041300 D1 DE60041300 D1 DE 60041300D1
Authority
DE
Germany
Prior art keywords
bus architecture
sequential bus
sequential
architecture
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60041300T
Other languages
English (en)
Inventor
Yoong-Chert Foo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE60041300D1 publication Critical patent/DE60041300D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60041300T 1999-04-29 2000-04-28 Sequentielle Bus-Architektur Expired - Lifetime DE60041300D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AUPQ0050A AUPQ005099A0 (en) 1999-04-29 1999-04-29 Sequential bus architecture

Publications (1)

Publication Number Publication Date
DE60041300D1 true DE60041300D1 (de) 2009-02-26

Family

ID=3814250

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60041300T Expired - Lifetime DE60041300D1 (de) 1999-04-29 2000-04-28 Sequentielle Bus-Architektur

Country Status (5)

Country Link
US (1) US6662256B1 (de)
EP (1) EP1049021B1 (de)
JP (1) JP4761487B2 (de)
AU (1) AUPQ005099A0 (de)
DE (1) DE60041300D1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934785B2 (en) * 2000-12-22 2005-08-23 Micron Technology, Inc. High speed interface with looped bus
US7032134B2 (en) * 2001-03-28 2006-04-18 Intel Corporation Microprocessor design support for computer system and platform validation
US20030172190A1 (en) * 2001-07-02 2003-09-11 Globespanvirata Incorporated Communications system using rings architecture
US7103008B2 (en) * 2001-07-02 2006-09-05 Conexant, Inc. Communications system using rings architecture
JP4838458B2 (ja) * 2001-09-13 2011-12-14 富士通セミコンダクター株式会社 半導体装置
KR100477641B1 (ko) * 2002-01-15 2005-03-23 삼성전자주식회사 버스 시스템 및 그 데이터 전송경로 결정방법
US7113488B2 (en) * 2002-04-24 2006-09-26 International Business Machines Corporation Reconfigurable circular bus
US7360007B2 (en) * 2002-08-30 2008-04-15 Intel Corporation System including a segmentable, shared bus
US20070027485A1 (en) * 2005-07-29 2007-02-01 Kallmyer Todd A Implantable medical device bus system and method
US20070076502A1 (en) * 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
KR101260632B1 (ko) 2005-09-30 2013-05-03 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US20080263248A1 (en) * 2007-04-20 2008-10-23 Harriman David J Multi-drop extension for a communication protocol
US9035957B1 (en) * 2007-08-15 2015-05-19 Nvidia Corporation Pipeline debug statistics system and method
DE102010003521A1 (de) * 2010-03-31 2011-10-06 Robert Bosch Gmbh Modulare Struktur zur Datenverarbeitung
EP2372490A1 (de) * 2010-03-31 2011-10-05 Robert Bosch GmbH Schaltungsanordnung für ein Datenverarbeitungssystem und Verfahren zur Datenverarbeitung
US11127110B2 (en) * 2017-03-01 2021-09-21 Arm Limited Data processing systems
CN111522757B (zh) * 2020-04-23 2023-08-22 上海琪云工业科技有限公司 一种基于i2c总线的中断读取与清除的控制方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378589A (en) * 1976-12-27 1983-03-29 International Business Machines Corporation Undirectional looped bus microcomputer architecture
US4263736A (en) * 1978-10-11 1981-04-28 Colorado Time Systems, Inc. Modular display system
US4356404A (en) * 1981-05-26 1982-10-26 Gte Automatic Electric Labs Inc. Circuit for equipping a variable number of bus units on a closed loop bus
US4641308A (en) * 1984-01-03 1987-02-03 Texas Instruments Incorporated Method of internal self-test of microprocessor using microcode
US4816993A (en) * 1984-12-24 1989-03-28 Hitachi, Ltd. Parallel processing computer including interconnected operation units
DE3603751A1 (de) * 1986-02-06 1987-08-13 Siemens Ag Informationsuebergabesystem zur uebergabe von binaeren informationen
FR2605768B1 (fr) * 1986-10-23 1989-05-05 Bull Sa Dispositif de commande de bus constitue par plusieurs segments isolables
US4916647A (en) * 1987-06-26 1990-04-10 Daisy Systems Corporation Hardwired pipeline processor for logic simulation
JPH0646413B2 (ja) * 1987-08-10 1994-06-15 日本電気株式会社 デ−タ処理プロセッサ
US5119481A (en) * 1987-12-22 1992-06-02 Kendall Square Research Corporation Register bus multiprocessor system with shift
JPH01274539A (ja) * 1988-04-27 1989-11-02 Fujitsu Ltd リングネットワーク
US5347515A (en) * 1992-03-27 1994-09-13 Pittway Corporation Method and apparatus for global polling having contention-based address identification
US5375097A (en) * 1993-06-29 1994-12-20 Reddy; Chitranjan N. Segmented bus architecture for improving speed in integrated circuit memories
GB9510509D0 (en) * 1995-05-24 1995-07-19 Thomson Consumer Electronics A digital data bus system including arbitration
JPH0991262A (ja) * 1995-09-20 1997-04-04 Fuji Xerox Co Ltd マルチプロセッサシステム
JP3202648B2 (ja) * 1997-04-11 2001-08-27 甲府日本電気株式会社 データ転送装置およびデータ転送システム

Also Published As

Publication number Publication date
EP1049021A2 (de) 2000-11-02
EP1049021B1 (de) 2009-01-07
EP1049021A3 (de) 2004-01-21
JP2001005776A (ja) 2001-01-12
US6662256B1 (en) 2003-12-09
JP4761487B2 (ja) 2011-08-31
AUPQ005099A0 (en) 1999-05-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition