DE60027902D1 - Verfahren und anordnung zur digitalen daten -soft-fehlerkorrektur - Google Patents

Verfahren und anordnung zur digitalen daten -soft-fehlerkorrektur

Info

Publication number
DE60027902D1
DE60027902D1 DE60027902T DE60027902T DE60027902D1 DE 60027902 D1 DE60027902 D1 DE 60027902D1 DE 60027902 T DE60027902 T DE 60027902T DE 60027902 T DE60027902 T DE 60027902T DE 60027902 D1 DE60027902 D1 DE 60027902D1
Authority
DE
Germany
Prior art keywords
arrangement
error correction
digital data
soft error
data soft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60027902T
Other languages
English (en)
Inventor
N Moudgal
Rick Hetherington
G Goldsbury
P Petry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE60027902D1 publication Critical patent/DE60027902D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60027902T 1999-08-17 2000-07-26 Verfahren und anordnung zur digitalen daten -soft-fehlerkorrektur Expired - Lifetime DE60027902D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/376,702 US6408417B1 (en) 1999-08-17 1999-08-17 Method and apparatus for correcting soft errors in digital data
PCT/US2000/020326 WO2001013234A1 (en) 1999-08-17 2000-07-26 Methods and apparatus for correcting soft errors in digital data

Publications (1)

Publication Number Publication Date
DE60027902D1 true DE60027902D1 (de) 2006-06-14

Family

ID=23486108

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60027902T Expired - Lifetime DE60027902D1 (de) 1999-08-17 2000-07-26 Verfahren und anordnung zur digitalen daten -soft-fehlerkorrektur

Country Status (6)

Country Link
US (1) US6408417B1 (de)
EP (1) EP1206739B1 (de)
JP (1) JP2004514184A (de)
KR (1) KR20020029925A (de)
DE (1) DE60027902D1 (de)
WO (1) WO2001013234A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546501B1 (en) * 1999-09-08 2003-04-08 Fujitsu Limited Cache memory apparatus and computer readable recording medium on which a program for controlling a cache memory is recorded
JP2002007225A (ja) * 2000-06-22 2002-01-11 Fujitsu Ltd アドレスパリティエラー処理方法並びに情報処理装置および記憶装置
US6700827B2 (en) 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
US7340659B2 (en) * 2002-05-15 2008-03-04 Infineon Technologies, A.G. Method of testing multiple modules on an integrated circuit
US7272773B2 (en) * 2003-04-17 2007-09-18 International Business Machines Corporation Cache directory array recovery mechanism to support special ECC stuck bit matrix
US7320096B2 (en) * 2003-05-09 2008-01-15 Hewlett-Packard Development Company, L.P. System and method for testing memory at full bandwidth
US7193876B1 (en) 2003-07-15 2007-03-20 Kee Park Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors
US6870749B1 (en) 2003-07-15 2005-03-22 Integrated Device Technology, Inc. Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
US6987684B1 (en) 2003-07-15 2006-01-17 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein
US7304875B1 (en) 2003-12-17 2007-12-04 Integrated Device Technology. Inc. Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
US7437597B1 (en) * 2005-05-18 2008-10-14 Azul Systems, Inc. Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
JP5010271B2 (ja) * 2006-12-27 2012-08-29 富士通株式会社 エラー訂正コード生成方法、およびメモリ制御装置
EP2169555A4 (de) * 2007-06-20 2011-01-05 Fujitsu Ltd Cache-steuerung, cache-steuerverfahren und cache-steuerprogramm
US8117497B1 (en) * 2008-11-17 2012-02-14 Xilinx, Inc. Method and apparatus for error upset detection and correction
CN101856912B (zh) * 2009-04-01 2013-05-22 精工爱普生株式会社 存储装置和包括能够与主机电路电连接的存储装置的系统
JP5663843B2 (ja) * 2009-04-01 2015-02-04 セイコーエプソン株式会社 記憶装置、基板、液体容器、不揮発性のデータ記憶部の制御方法、ホスト回路と着脱可能な記憶装置を含むシステム
US8645796B2 (en) 2010-06-24 2014-02-04 International Business Machines Corporation Dynamic pipeline cache error correction
US8553441B1 (en) 2010-08-31 2013-10-08 Netlogic Microsystems, Inc. Ternary content addressable memory cell having two transistor pull-down stack
US8462532B1 (en) 2010-08-31 2013-06-11 Netlogic Microsystems, Inc. Fast quaternary content addressable memory cell
US8625320B1 (en) 2010-08-31 2014-01-07 Netlogic Microsystems, Inc. Quaternary content addressable memory cell having one transistor pull-down stack
US8582338B1 (en) 2010-08-31 2013-11-12 Netlogic Microsystems, Inc. Ternary content addressable memory cell having single transistor pull-down stack
US8837188B1 (en) 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3744023A (en) * 1971-05-17 1973-07-03 Storage Technology Corp Detection and correction of phase encoded data
US4604750A (en) * 1983-11-07 1986-08-05 Digital Equipment Corporation Pipeline error correction
DE3379192D1 (en) 1983-12-19 1989-03-16 Itt Ind Gmbh Deutsche Correction method for symbol errors in video/teletext signals
US4617664A (en) 1984-06-29 1986-10-14 International Business Machines Corporation Error correction for multiple bit output chips
DE3431770A1 (de) 1984-08-29 1986-03-13 Siemens AG, 1000 Berlin und 8000 München Verfahren und anordnung zur sicherung von wichtigen informationen in speichereinheiten mit wahlweisem zugriff, insbesondere solchen aus ram-bausteinen
US5233616A (en) * 1990-10-01 1993-08-03 Digital Equipment Corporation Write-back cache with ECC protection
DE59008549D1 (de) * 1990-12-18 1995-03-30 Siemens Nixdorf Inf Syst Verfahren und Schaltungsanordnung zur Datensicherung in Speichereinheiten.
US5784548A (en) * 1996-03-08 1998-07-21 Mylex Corporation Modular mirrored cache memory battery backup system
KR100190377B1 (ko) * 1996-11-07 1999-06-01 김영환 마이크로 프로세서의 버스 인터페이스 유닛
US6304992B1 (en) * 1998-09-24 2001-10-16 Sun Microsystems, Inc. Technique for correcting single-bit errors in caches with sub-block parity bits

Also Published As

Publication number Publication date
KR20020029925A (ko) 2002-04-20
WO2001013234A1 (en) 2001-02-22
EP1206739B1 (de) 2006-05-10
US6408417B1 (en) 2002-06-18
EP1206739A1 (de) 2002-05-22
JP2004514184A (ja) 2004-05-13

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Legal Events

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