DE60023002T2 - Erweiterung und abbildung auf physikalischem speicher von linearen adressen unter verwendung von 4 und 8 byte seitentabelleneinträgen in einem 32-bit mikroprozessor - Google Patents

Erweiterung und abbildung auf physikalischem speicher von linearen adressen unter verwendung von 4 und 8 byte seitentabelleneinträgen in einem 32-bit mikroprozessor Download PDF

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Publication number
DE60023002T2
DE60023002T2 DE60023002T DE60023002T DE60023002T2 DE 60023002 T2 DE60023002 T2 DE 60023002T2 DE 60023002 T DE60023002 T DE 60023002T DE 60023002 T DE60023002 T DE 60023002T DE 60023002 T2 DE60023002 T2 DE 60023002T2
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DE60023002D1 (de
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Shahrokh Shahidzadeh
E. Bryant BIGBEE
B. David PAPWORTH
Frank Binns
P. Robert COLWELL
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
DE60023002T 1999-03-12 2000-02-29 Erweiterung und abbildung auf physikalischem speicher von linearen adressen unter verwendung von 4 und 8 byte seitentabelleneinträgen in einem 32-bit mikroprozessor Expired - Lifetime DE60023002T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/267,796 US6349380B1 (en) 1999-03-12 1999-03-12 Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
PCT/US2000/005420 WO2000055723A1 (en) 1999-03-12 2000-02-29 Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
US267796 2002-10-09

Publications (2)

Publication Number Publication Date
DE60023002D1 DE60023002D1 (de) 2006-02-16
DE60023002T2 true DE60023002T2 (de) 2006-07-20

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DE60023002T Expired - Lifetime DE60023002T2 (de) 1999-03-12 2000-02-29 Erweiterung und abbildung auf physikalischem speicher von linearen adressen unter verwendung von 4 und 8 byte seitentabelleneinträgen in einem 32-bit mikroprozessor

Country Status (8)

Country Link
US (1) US6349380B1 (https=)
EP (1) EP1188113B1 (https=)
JP (1) JP4593792B2 (https=)
CN (1) CN1149473C (https=)
AU (1) AU3390900A (https=)
DE (1) DE60023002T2 (https=)
HK (1) HK1043215B (https=)
WO (1) WO2000055723A1 (https=)

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Also Published As

Publication number Publication date
EP1188113B1 (en) 2005-10-05
HK1043215B (en) 2006-04-28
AU3390900A (en) 2000-10-04
US6349380B1 (en) 2002-02-19
JP2002539555A (ja) 2002-11-19
DE60023002D1 (de) 2006-02-16
EP1188113A1 (en) 2002-03-20
HK1043215A1 (en) 2002-09-06
JP4593792B2 (ja) 2010-12-08
CN1149473C (zh) 2004-05-12
CN1343332A (zh) 2002-04-03
WO2000055723A1 (en) 2000-09-21

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Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806