US8671287B2 - Redundant power supply configuration for a data center - Google Patents

Redundant power supply configuration for a data center Download PDF

Info

Publication number
US8671287B2
US8671287B2 US12/821,226 US82122610A US8671287B2 US 8671287 B2 US8671287 B2 US 8671287B2 US 82122610 A US82122610 A US 82122610A US 8671287 B2 US8671287 B2 US 8671287B2
Authority
US
United States
Prior art keywords
power supplies
high current
plurality
power
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US12/821,226
Other versions
US20110320796A1 (en
Inventor
Casimer M. DeCusatis
Rajaram B. Krishnamurthy
Michael Onghena
Anuradha Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US12/821,226 priority Critical patent/US8671287B2/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAO, ANURADHA, DECUSATIS, CASIMER M., ONGHENA, MICHAEL, KRISHNAMURTHY, RAJARAM B.
Publication of US20110320796A1 publication Critical patent/US20110320796A1/en
Application granted granted Critical
Publication of US8671287B2 publication Critical patent/US8671287B2/en
Application status is Expired - Fee Related legal-status Critical
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • G06F1/206Cooling means comprising thermal management
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10Parallel operation of dc sources
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/14Mounting supporting structure in casing or on frame or rack
    • H05K7/1485Servers; Data center rooms, e.g. 19-inch computer racks
    • H05K7/1488Cabinets therefore, e.g. chassis, racks
    • H05K7/1492Cabinets therefore, e.g. chassis, racks having electrical distribution arrangements, e.g. power supply or data communications
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T307/00Electrical transmission or interconnection systems
    • Y10T307/50Plural supply circuits or sources
    • Y10T307/549Load current control

Abstract

A redundant power supply configuration for a data center is provided. A method includes receiving instructions to operate power supplies at a high current mode. An individual current for each of the power supplies is calculated to total a high current at the high current mode. The power supplies are operated at the high current mode to provide the high current at the high current mode. In response to operation at the high current mode being complete, the power supplies are operated at a normal mode to provide a normal current at the normal current mode.

Description

BACKGROUND

Exemplary embodiments relate generally to redundant power supplies, and more particularly to power management of redundant power supplies.

There are significant industry-wide concerns with energy consumption in modern data centers. A data center or datacenter, also called a server farm, is a facility used to house computer systems and associated components, such as telecommunications and storage systems. It generally includes redundant or backup power supplies, redundant data communications connections, environmental controls (e.g., air conditioning, fire suppression) and security devices. The cost of providing electrical power to a data center has become a dominant purchasing consideration, which many consider to be more significant than the cost of the actual hardware, software, and management services. Recent industry reports indicate that data center power consumption has doubled in the past 5 years, and will double again in the next 5 years unless steps are taken to mitigate this trend. Recognizing this, IBM® and many other companies have begun “green” or environmentally friendly initiatives.

BRIEF SUMMARY

An exemplary embodiment provides a method for power supply operation. An instruction is received to operate power supplies at a high current mode. An individual current for each of the power supplies is calculated to total a high current at the high current mode. The power supplies are operated at the high current mode to provide the high current at the high current mode. In response to operation at the high current mode being complete, the power supplies are operated at a normal mode to provide a normal current at the normal current mode.

An addition exemplary embodiments provides a power system. The power system includes power supplies configured to provide redundant power a power manager configured to control the power supplies. The power manager is configured to receive an instruction to operate the power supplies at a high current mode, calculate an individual current for each of the power supplies in which a total of the individual current amounts to a high current at the high current mode, operate the power supplies at the high current mode to provide the high current. In response to operation at the high current mode being complete, the power manager is configured to operate the power supplies at a normal mode to provide a normal current at the normal mode.

A further exemplary embodiment provides a computer program product, tangibly embodied on a computer readable medium, and the computer program product includes instructions for causing a computer to execute a method for power supply operation. An instruction is received to operate power supplies at a high current mode. An individual current for each of the power supplies is calculated to total a high current at the high current mode. The power supplies are operated at the high current mode to provide the high current at the high current mode. In response to operation at the high current mode being complete, the power supplies are operated at a normal mode to provide a normal current at the normal current mode.

Additional features and details are realized through the techniques of the present invention. Other embodiments and features are described in detail herein and are considered a part of the claimed invention. For a better understanding of features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:

FIG. 1 depicts a block diagram of a system in accordance with exemplary embodiments;

FIG. 2 depicts a flow chart in accordance with exemplary embodiments;

FIG. 3 depicts a computer that may utilized to implement exemplary embodiments; and

FIG. 4 depicts a computer program product that may be implemented by an exemplary embodiment.

DETAILED DESCRIPTION

Exemplary embodiments are configured to exploit many opportunities to not only make more efficient use of energy in servers and storage devices, but to improve the response time of these systems. Current storage controllers use a digitally controlled power supply capable of producing many different levels of output current. For redundancy and high availability, at least two power supplies are configured for each system. Recent IBM® storage control units employ an N+1=3 design point, with 3 redundant power supplies, to insure there is never a single point of failure in the power distribution system. However, current power supply designs may not utilize the redundant power supplies to their full potential, resulting in all the power supplies running at suboptimal efficiency. In accordance with exemplary embodiments, it is possible to use the excess capacity of the N+1 power supplies to achieve higher drive currents, which means more efficient operating points and faster spin-up times for disk storage.

Exemplary embodiments provide a method and apparatus to utilize excess capacity available in redundant power supplies to achieve higher drive currents. This results in the power supplies operating at higher overall efficiency, as well as providing faster start-up for disk storage for higher performance in accordance with exemplary embodiments.

FIG. 1 depicts a block diagram 100 illustrating a system in accordance with exemplary embodiments.

In the block diagram 100, a server 10 is operatively connected to a power supply system 80. The server includes the hardware and software to operate as a server as understood by one skilled in the art. The power supply system 80 includes a power supply master control 30 that is configured to control a plurality of redundant power supplies 50. There may be 1 to N redundant power supplies 50, where N represents the last power supply 50. Each redundant power supply 50 includes a microcontroller 60 and a feedback controller 40. A microcontroller (also microcomputer, MCU or μC) may be a small computer on a single integrated circuit consisting internally of a relatively simple central processing unit (CPU), clock, timers, input/output (I/O ports, and memory. Program memory is also often included on chip. Microcontrollers are designed for small or dedicated applications. They will generally have the ability to retain functionality while waiting for an event such as a button press or other interrupt; power consumption while sleeping (CPU clock and most peripherals off) may be just nanowatts, making many of them well suited for long lasting battery applications. Other microcontrollers may serve performance-critical roles, where they may need to act more like a digital signal processor (DSP), with higher clock speeds and power consumption.

Note that although each redundant power supply 50 has its own microcontroller 60 for controlling the power supply 50, the functionality of the individual microcontrollers 60 may optionally be implemented in one central microcontroller 60 a (shown with dashed lines) for all the power supplies 50, and the central power supply 60 a may be included in the power supply master control 30. In exemplary embodiments, any discussion for the microcontroller 60 can apply to the central microcontroller 60 a. Also, note that each power supply 50 is configured to output power and comprises all the software and hardware to operate as a power supply as understood by one by one skilled in the art.

The server 10 and the power supply system 80 may be operatively connected to one or more storage devices 70. As understood by one skilled in the art, the storage device 70 may include a storage control unit 72 that is configured to control data volumes 74. The volumes 74 may include disks for storing (recording) the data. Disk storage or disc storage is a general category of storage mechanisms, in which data are digitally recorded by various electronic, magnetic, optical, or mechanical methods on a surface layer deposited on one or more planar, round, and rotating platters. The storage device 70 includes a disk drive which may have a mechanical arm or mechanism for accessing the disks, such as for reading and writing (storage). The disks 74 spin by receiving power from the power supply system 80. For example, the storage device 70 may include the features of a direct access storage device (DASD).

A software component such as a power management hypervisor 20 is configured to request and manage power needed to run the storage device 70. The power management hypervisor 20 instructs the power supply master control 30 of the power needs for the storage device 70. The power supply master control 30 instructs the power supplies 50 to supply power to the storage device 70 at the appropriate times.

For example, the power supply system 80 may employ 3 redundant power supplies 50 under digital control of the power supply master control 30, such that each redundant power supply 50 is operational all of the time. In this manner, failure of a single power supply 50 will not disrupt operation of the storage device 70, and the remaining power supplies 50 are designed to automatically pick up the excess power load required to keep the storage device 70 operational. One power supply such as the power supply 50, typically drives a maximum of 120 amps, and is programmable with 12-24 discrete output current levels, adjustable in 0.1 amp increments. For example, disk storage controllers (such as the storage control unit 72) may require a total of 2.722 kW with 14 adjustable output levels, or 1.806 kW with 18 output levels. In the normal mode, each power supply 50 in a redundant configuration runs at 20-25% of its peak load, which means the power supply is operating at about 60% efficiency. It is understood that some power supplies 50 may run somewhat less or more than the 20-25%, but the present disclosure notes this range at about ¼ of its peak load (which is ¼ of its maximum capacity or ¼ of its peak current).

However, in high current output mode (or high current mode), exemplary embodiments are configured to increase the efficiency for the power supplies 50 by modifying the firmware (or software) of the power supply master control 30 and the firmware (or software) of the microcontroller 60, such that each power supply 50 runs at (and/or near) 100% of its peak efficiency point (35%-70% of maximum capacity); even if the power supply 50 runs at less than 100% of its peak load it is understood that this still refers to running at high current output mode. Higher efficiencies are achieved with output currents that are in 35%-70% maximum output capacity of the power supplies 50. In exemplary embodiments, the firmware (of the power supply master control 30) controlling the power supplies 50 is reprogrammed to provide higher output current to the storage device 70 under certain conditions, for example, during spin-up of the disks 74 from a reboot and/or spin-up from a quiescent state. The quiescent state is when the disks 74 are at rest (i.e., not spinning). When the power supply master control 30 communicates with the microcontrollers 60 to cause the (three) redundant power supplies 50 to output high currents (peak currents), the power supply system 80 is operating in high current output mode (or high current mode).

One skilled in the art understands the relationship between power (P), current (I), volts (V), and resistance (R)/impedance (Z). Note that high current mode is utilized for explanation purposes and exemplary embodiments may have high voltage mode, high power mode, etc. Also, running the power supplies 50 at 100% of their peak (maximum) efficiency point (e.g., 50%-70% of their maximum capacity) is not meant to be limiting. For example, there may be power supplies 50 that have a maximum efficiency point at 45% of their load, and the maximum efficiency point is the load at which the power supply 50 operates with the lowest losses. So there may be power supplies 50 that each have a 100 ampere (amp) maximum current, and the maximum efficiency point for each power supply 50 is at 50 amps. Accordingly, when the power supply master control 30 instructs the microcontrollers 60 to drive each power supply 50 at its maximum efficiency point (which is 50% in this example) at the high current mode, each respective microcontroller 60 causes its power supply 50 to output 50 amps of current. If those same power supplies 50 had a maximum efficiency point at 70% of its load, the microcontrollers 60 would then drive each respective power supply 50 at 70 amps of current. It is understood that during the high current mode each power supply 50 may operate at a range of its maximum efficiency point, such as plus or minus (+/−) 20% of its maximum efficiency point. Even though examples may be utilized in which the power supplies 50 operate at different maximum (peak) efficiency points (where the maximum efficiency point is at, e.g. 50% of its peak current), it is understood that exemplary embodiments apply to power supplies 50 that operate at other maximum efficiency points and the present disclosure is not meant to be limited to power supplies 50 that only have a maximum efficiency point (in the range of) 50% of its peak current. For example, a high efficiency range for the power supplies 50 to operate is 35%-70% of peak current, and a higher efficiency range for the power supplies 50 to operate is 45%-50% of peak current.

When operating in the high current output mode, the power supplies 50 may not have enough excess capacity to provide fully redundant backup for each other; however, the power supplies 50 can deliver improved efficiency. The currents required in high current mode are within the capacity of current power supplies, which can deliver current steps up to 100 amps (or 100% of their load). At the higher output currents of the high current mode, the power supply 50 can achieve close to 95% efficiency; the heat generated while operating in this high current mode is actually less than when the power supply 50 is running at only 20% of its peak load (which is considered the normal mode), and thus the cooling requirement is reduced. Since the redundant power supplies 50 are designed to operate up to these maximum levels (as operated in the high current mode), there is no impact on their performance or individual reliability.

Moreover, in the high current mode, the increased power supply current of the redundant power supplies 50 allows disk storage 74 of the storage device 70 to spin up more quickly from a quiescent state. The start-up time for a storage disk 74 is roughly proportional to the disk drive current received from the power supplies 50; by the power supply master control 30 doubling the drive current provided to the storage device 70 in the high current mode, for example, the time to spin-up the disks 74 to operational speed is reduced by half. By modifying the power supply master control 30 and/or the microcontrollers 60 to run the power supplies 50 at maximum efficiency point current (i.e., 40%-70% of its peak current) in high current mode, exemplary embodiments make it possible to boot up a storage disk 74 from a cold start 25-50% faster than conventional methods, at the same time consuming less total power due to the higher operating efficiency of the power supplies 50. A cold start is when the rotating disks 74 are at rest (e.g., the quiescent state). In the unlikely event of a power supply component failure during boot, the power supply master control 30 and/or the microcontroller 60 reconfigures the remaining power supplies 50 to continue the boot operation (of the storage device 70) uninterrupted, but using lower currents and therefore taking more time. In the high current mode, the ability to recover more rapidly from a quiescent state means that the power management hypervisor 20 is able to take the storage device 70 into quiescent states more frequently, thereby saving additional power over long periods of use. In other words, the power management hypervisor 20 is configured to stop the disks 70 from spinning more frequently to save power. For example, an archival storage device 70 may not be utilized as often as a main storage device 70, and since the power management hypervisor 20 can request that the power supply master control 30 provide power to the archival storage device 70 in the high current mode, the power management hypervisor 20 does not have to worry about a lag in spin-up time since the high current mode can boot up the disks 74 of the archival storage device 70 much faster than boot-up in a normal mode.

Additional features of exemplary embodiments include the feedback control 40, which may be implemented in software and/or hardware. The feedback control 40 of the power supply 50 provides additional ability to the microcontroller 60 for monitoring power supply levels for current spikes and voltage spikes which may result from the additional switching from the normal mode to high current mode described in the present disclosure. Since all the power supplies 50 are designed to be capable of current steps at 25% of their peak load, this is not expected to be a concern. However, the feedback control 40 provides a closed-loop control system to allow early detection of instabilities by the microcontroller 60 and allows the microcontroller 60 to shut down the high current operation mode before any adverse effects occur to the power supply 50. Each power supply 50 is shown with its own feedback control 40 but it is understood that a central feedback control 40 a could be included in the power supply monitor control 30 to monitor all power supplies 50. In exemplary embodiments, the feedback control 40 measures the feedback coming from the load of the storage device 40 and monitors for voltage spikes and current spikes, and if a voltage spike and/or current spike is too high for a certain period of time, the feedback control 40 causes the microcontroller 60 to ramp down the voltage and/or current for that particular power supply 50.

An additional feature of the power supply master control 30 is the ability to divide the higher operating current (which could also be power and/or voltage) equally across the power supply levels of all the power supplies 50, so that each power supply 50 never exceeds the individual current limits of a given level for each power supply 50. For example, if the power supply system 80 is using an N+1=3 design, then the maximum bring-up current delta (which is the high current in high current mode being requested by the hypervisor 20) will be divided evenly among all three power supplies 50. The following example is provided to illustrate an implementation of the high current mode.

First, the power supply master control 30 may poll each microcontroller 60 for its present output current (e.g., at 30-33% of its maximum capacity during normal mode) and voltage levels as well as the microcontroller's maximum output current limit. The microcontrollers 60 control the current output for its respective power supply 50. The power supply master control 30 receives (and stores) from each microcontroller 60 the present current output (which may be, e.g., 25% of its maximum) and the maximum current output (which would be available for high current mode) of each power supply 50. At some subsequent point in time, the power supply master control 30 may receive a command from the power management hypervisor 20 to restart the disks 74 of the storage device from a quiescent state using higher current levels of the high current mode. The (firmware of the) power supply master control 30 calculates the respective current load draw for each power supply 50 and instructs the microcontrollers 60 to increase their current proportional to these limits, by dividing the maximum current delta across all N available power supplies 50 and levels equally.

As an illustration using fictitious values, 3 microcontrollers 60 of redundant power supplies 50 may be presently (in normal mode) operating at 30% which is 3 amps, and each of the 3 microcontrollers 60 has a maximum 100% output current of 10 amps (e.g., in high current mode); this information is passed to the power supply master control 30. When the hypervisor 20 requests the high output mode (with a total current of 18 amps) to start the start the disks 74 from rest, the power supply master control 30 is configured to calculate the respective current load for each of the 3 individual microcontrollers 60 by dividing the requested 18 amps by 3 (which is the number of redundant power supplies 50). As such, each microcontroller 60 would be requested (by the power supply master control 30) to increase their respective current output by 3 amps to result in an output current of 6 amps for the high current mode. In high current mode, the power supply master control 30 would cause the 3 power supplies 50 (via the microcontroller 60) to provide at total of 18 amps to the storage device 70, with each power supply 50 providing 6 amps (which is 60% of their maximum current output). If the fictitious total current requested by the hypervisor 20 was 21 amps, the power supply master control 30 would divide the total by 3 and cause the 3 power supplies 50 to each provide 7 amps of current in the high current mode.

Now back to the example, while the power supply levels adjust to meet the high current output of the high current mode, each microcontroller 60 monitors their respective power supply 50 for current spikes and/or spurious states using the closed loop feedback control 40; this allows the high current mode for any one or all of the respective power supplies 50 to be terminated by the microcontroller 60 if early signs of instability are measured. Otherwise, the high current mode is maintained for a predetermined time (e.g., several minutes or more) before the power supply master control 30 instructs the power supplies 50 (i.e., via the microcontroller 60) to return to their normal mode of redundant operation. For the brief period during the high current mode, the power supply master control 30 may not operate the power supplies 50 in a redundant configuration where backup is available. Once the system boot (and/or any other predefined event) of the storage device 70 is complete, the hypervisor 20 instructs the power supply master control 30 to return to normal mode. The power supply master control 30 reconfigures (via the microcontrollers 60) the power supplies 50 to their normal redundant operation.

Also, in exemplary embodiments, the power supplies 50 could be reconfigured by the power supply master control 30 on demand to run in higher current mode for short periods, for example, in response to high workload conditions for the storage device 70. Accordingly, the power management hypervisor 20 can request current for the high current output mode to the power supply master control 30 at predefined conditions, and the power supply master control 30 calculates the respective current requirements for each individual microcontroller 60 by dividing the total requested current by the available (e.g., 3) power supplies 50.

Note that the power supplies 50 are always tested at their maximum ratings for electromagnetic compatibility (EMC) compliance, so there are no EMC related issues associated with the proposed operation of exemplary embodiments. This approach of exemplary embodiments has the potential to provide faster returns to normal operation following a quiescent period for disk storage (and/or to provide faster system boot from a cold start). Also, as discussed herein, energy is saved in several ways. First, the ability to recovery faster from a quiescent state means that the hypervisor 20 can put the storage device 70 into quiescent states more frequently. Second, when in high current mode, the power supplies 50 operate at higher efficiency with reduced cooling requirements. By the present disclosure, one skilled in the art understands that exemplary embodiments provide features that may be utilized in other storage and server equipment by various manufacturers.

FIG. 2 illustrates a flow chart 200 in accordance with exemplary embodiments.

At operation 205, the power supply master control 30 is configured to receive instructions to operate the power supplies 50 at a high current mode. For example, the hypervisor 20 may request a certain amount X of high current in the high current mode to spin-up and/or boot-up the disks 74 and the power supply master control 30 determines if it can meet this request. The power supply master control 30 obtains the present amount of current that each power supply 50 is outputting, which should be roughly ¼ of its maximum capacity, and obtains the maximum amount of current that each power supply 50 can output. With this information the power supply master control 30 determine how to divide the requirement for X amount of high current among the power supplies.

At operation 210, the power supply master control 30 is configured to calculate an individual current that is required for each the power supplies 50 such that the total of the individual current equals the high current (X) in the high current mode. If there are 3 power supplies 50, the power supply master control 30 cause each power supply 50 to output individual current in the amount A, such that individual currents A+A+A=X which is the high current amount.

At operation 215, the power supply master control 30 is configured to operate the power supplies 50 at the high current mode to provide the X amount of high current at the high current mode to the storage device 70.

In response to operation at the high current mode being complete such as when the disks 74 spin-up to a nominal speed, the power supply master control 30 is configured to operate the power supplies 50 at a normal mode to provide a normal amount (Y) of current to the storage device 70.

Further, when the power supply master control 30 obtains the 3 present current output for each individual power supply 50, the power supply master control 30 causes each of the 3 power supplies to individually increase their present current outputs to the calculated individual current (A) respectively, such that the total of the individual current provides the X amount of high current at the high current mode. When operating the power supplies 50 at the high current mode to provide the X amount of high current, the high current mode causes the power supplies 50 to operate more efficiently than the normal mode, and/or operate at a lower temperature than the normal mode. When operating the power supplies 50 at the high current mode to provide the high current, the operating in the high current mode causes the power supplies 50 to briefly stop operating in a redundant power supply configuration. When the brief time in the high current mode is over (such as when the disks 74 reach a nominal operating speed of a certain amount of revolutions per minute (RPM)) and/or after a predefined amount of time (e.g., after several minutes), the power supply master control 30 can instruct the microcontrollers 60 to return to normal mode which is the redundant power supply configuration. Also, the power supply master control 30 may receive an indication to return to normal mode from the hypervisor 20 because the disks 74 have reached the nominal operating speed.

FIG. 3 illustrates an example of a computer 300 having capabilities, which may be included in exemplary embodiments. Various methods, procedures, modules, flow diagrams, tables, and techniques discussed herein may also incorporate and/or utilize the capabilities of the computer 300. Moreover, capabilities of the computer 300 may be utilized to implement features of exemplary embodiments discussed herein. One or more of the capabilities of the computer 300 may implement and/or complement any element discussed herein.

Generally, in terms of hardware architecture, the computer 300 may include one or more processors 310, computer readable storage memory 320, and one or more input and/or output (I/O) devices 370 that are communicatively coupled via a local interface (not shown). The local interface can be, for example but not limited to, one or more buses or other wired or wireless connections, as is known in the art. The local interface may have additional elements, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface may include address, control, and/or data connections to enable appropriate communications among the aforementioned components.

The processor 310 is a hardware device for executing software that can be stored in the memory 320. The processor 310 can be virtually any custom made or commercially available processor, a central processing unit (CPU), a data signal processor (DSP), or an auxiliary processor among several processors associated with the computer 300, and the processor 310 may be a semiconductor based microprocessor (in the form of a microchip) or a macroprocessor.

The computer readable memory 320 can include any one or combination of volatile memory elements (e.g., random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cassette or the like, etc.). Moreover, the memory 320 may incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory 320 can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor 310.

The software in the computer readable memory 320 may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. The software in the memory 320 includes a suitable operating system (O/S) 350, compiler 340, source code 330, and one or more applications 360 of the exemplary embodiments. As illustrated, the application 360 comprises numerous functional components for implementing the features, processes, methods, functions, and operations of the exemplary embodiments. The application 360 of the computer 300 may represent numerous applications, agents, software components, modules, interfaces, controllers, etc., as discussed herein but the application 360 is not meant to be a limitation. The operating system 350 may control the execution of other computer programs, and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

The application(s) 360 may employ a service-oriented architecture, which may be a collection of services that communicate with each. Also, the service-oriented architecture allows two or more services to coordinate and/or perform activities (e.g., on behalf of one another). Each interaction between services can be self-contained and loosely coupled, so that each interaction is independent of any other interaction. Further, the application 360 may be a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed. When a source program, then the program is usually translated via a compiler (such as the compiler 340), assembler, interpreter, or the like, which may or may not be included within the memory 320, so as to operate properly in connection with the O/S 350. Furthermore, the application 360 can be written as (a) an object oriented programming language, which has classes of data and methods, or (b) a procedure programming language, which has routines, subroutines, and/or functions.

The I/O devices 370 may include input devices (or peripherals) such as, for example but not limited to, a mouse, keyboard, scanner, microphone, camera, etc. Furthermore, the I/O devices 370 may also include output devices (or peripherals), for example but not limited to, a printer, display, etc. Finally, the I/O devices 370 may further include devices that communicate both inputs and outputs, for instance but not limited to, a NIC or modulator/demodulator (for accessing remote devices, other files, devices, systems, or a network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, etc. The I/O devices 370 also include components for communicating over various networks, such as the Internet or an intranet. The I/O devices 370 may be connected to and/or communicate with the processor 310 utilizing Bluetooth connections and cables (via, e.g., Universal Serial Bus (USB) ports, serial ports, parallel ports, FireWire, HDMI (High-Definition Multimedia Interface), etc.).

When the computer 300 is in operation, the processor 310 is configured to execute software stored within the memory 320, to communicate data to and from the memory 320, and to generally control operations of the computer 300 pursuant to the software. The application 360 and the O/S 350 are read, in whole or in part, by the processor 310, perhaps buffered within the processor 310, and then executed.

When the application 360 is implemented in software it should be noted that the application 360 can be stored on virtually any computer readable storage medium for use by or in connection with any computer related system or method. In the context of this document, a computer readable storage medium may be an electronic, magnetic, optical, or other physical device or means that can contain or store a computer program for use by or in connection with a computer related system or method.

The application 360 can be embodied in any computer-readable medium 320 for use by or in connection with an instruction execution system, apparatus, server, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable storage medium” can be any means that can store, read, write, communicate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, or semiconductor system, apparatus, or device.

In exemplary embodiments, where the application 360 is implemented in hardware, the application 360 can be implemented with any one or a combination of the following technologies, which are each well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Further, as will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

As described above, embodiments can be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. In exemplary embodiments, the invention is embodied in computer program code executed by one or more network elements. Embodiments include a computer program product 400 as depicted in FIG. 4 on a computer usable medium 402 with computer program code logic 404 containing instructions embodied in tangible media as an article of manufacture. Exemplary articles of manufacture for computer usable medium 402 may include floppy diskettes, CD-ROMs, hard drives, universal serial bus (USB) flash drives, or any other computer-readable storage medium, wherein, when the computer program code logic 404 is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. Embodiments include computer program code logic 404, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code logic 404 is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code logic 404 segments configure the microprocessor to create specific logic circuits.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims (16)

The invention claimed is:
1. A method for power supply operation, comprising:
receiving an instruction to operate a plurality of power supplies at a high current mode, each of the power supplies comprises an individual feedback controller;
wherein the power supplies are redundant and serve as backups to one another to ensure that there is not a single point of failure as a redundant power supply configuration;
wherein the power supplies are connected to a storage device having planar disks for reading and writing data;
calculating an individual current for each of the plurality of power supplies to total a high current at the high current mode;
operating the plurality of power supplies at the high current mode to provide the high current at the high current mode to the storage device having the planar disks for reading and writing data;
in response to operation at the high current mode being complete, operating the plurality of power supplies at a normal mode to provide a normal current at the normal mode;
wherein operating the plurality of power supplies to supply the high current of the high current mode while causing the plurality of power supplies to operate at a higher efficiency than the normal mode and operate at a lower temperature than the normal mode, each of the plurality of power supplies that operate at the lower temperature while supplying the high current;
the plurality of power supplies increasing output to a load to operate at the lower temperature while supplying the high current of the high current mode;
wherein operating the plurality of power supplies to supply the high current at the high current mode occurs when booting up the planar disks of the storage device, which results in stopping the plurality of power supplies from operating in the redundant power supply configuration to the storage device such that the power supplies are no longer redundant and do not serve as backups to one another;
wherein operating the plurality of power supplies to supply the high current at the high current mode occurs when starting the planar disks of the storage device from rest, which results in stopping the plurality of power supplies from operating in the redundant power supply configuration to the storage device such that the power supplies are no longer redundant and do not serve as backups to one another;
wherein operating the plurality of power supplies to supply the high current at the high current mode occurs when demand for the storage device is high, which results in stopping the plurality of power supplies from operating in the redundant power supply configuration to the storage device such that the power supplies are no longer redundant and do not serve as backups to one another; and
wherein operating the plurality of power supplies at the normal mode to provide the normal current causes the plurality of power supplies to again start operating in the redundant power supply configuration.
2. The method of claim 1, wherein a power manager receives the instruction for the high current mode; and
wherein the power manager calculates the individual current for each of the plurality of power supplies by dividing the high current by a number of the plurality of power supplies.
3. The method of claim 1, wherein calculating the high current at the high current mode for each of the plurality of power supplies comprises:
obtaining a maximum current rating in high efficiency range for each of the plurality of power supplies;
causing the total of the individual current for each of the plurality of power supplies to equally sum to the high current at the high current mode without exceeding the maximum current rating in the high efficiency range for any one of the plurality of power supplies.
4. The method of claim 1, wherein calculating the high current at the high current mode for each of the plurality of power supplies comprises:
obtaining present current outputs for each of the plurality of power supplies;
dividing the high current by a number of the plurality of power supplies to determine the individual current for each of the plurality of power supplies; and
causing each of the plurality of power supplies to individually increase present current outputs to the individual current respectively, such that the total of the individual current provides the high current at the high current mode.
5. The method of claim 1, wherein the high current mode operates each of the power supplies in a range of its respective maximum current.
6. The method of claim 1, wherein a power manager divides the high current at the high current mode among the plurality of power supplies, such that no one of the plurality of power supplies exceeds it maximum current capacity in high efficiency range; and
wherein when no one of the plurality of power supplies will exceed its maximum capacity in the high efficiency range, the power manager divides the high current at the high current mode equally among the plurality of power supplies.
7. The method of claim 1, wherein the plurality of power supplies are redundant power supplies;
wherein in the normal mode each of the plurality of power supplies individually operates in a region of one-fourth of maximum capacity; and
wherein in the high current mode each of the plurality of power supplies individually operates in a region of maximum current in high efficiency range.
8. The method of claim 1, further comprising in response to operating the plurality of power supplies in the high current mode, taking the storage device into quiescent states more frequently in which disks of the storage device stop spinning.
9. The method of claim 1, wherein operating the plurality of power supplies at the high current mode is configured to cause the storage device receiving the high current to:
spin-up faster from rest than in the normal mode; and
boot-up faster than in the normal mode.
10. The method of claim 1, wherein a feedback control monitors the plurality of power supplies to detect current spikes and voltage spikes when operating at the high current mode; and
wherein the feedback control causes the plurality of power supplies to exit the high current mode when current spikes or voltage spikes are detected for a predefined time.
11. A power system, comprising:
power supplies configured to provide redundant power, each of the power supplies comprises an individual feedback controller;
wherein the power supplies are redundant and serve as backups to one another to ensure that there is not a single point of failure as a redundant power supply configuration;
wherein the power supplies are connected to a storage device having planar disks for reading and writing data; and
a power manager configured to control the power supplies, wherein the power manager is configured to:
receive an instruction to operate the power supplies at a high current mode;
calculate an individual current for each of the power supplies in which a total of the individual current amounts to a high current at the high current mode;
operate the power supplies at the high current mode to provide the high current to the storage device having the planar disks for reading and writing data; and
in response to operation at the high current mode being complete, operate the power supplies at a normal mode to provide a normal current at the normal mode;
wherein operating the power supplies to supply the high current of the high current mode while causing the power supplies to operate at a higher efficiency than the normal mode and operate at a lower temperature than the normal mode, each of the power supplies that operate at the lower temperate while supplying the high current;
the power supplies increasing output to the storage device having the planar disks to operate at the lower temperature while supplying the high current of the high current mode;
wherein operating the plurality of power supplies to supply the high current at the high current mode occurs when booting up the planar disks of the storage device, which results in stopping the plurality of power supplies from operating in the redundant power supply configuration to the storage device such that the power supplies are no longer redundant and do not serve as backups to one another;
wherein operating the plurality of power supplies to supply the high current at the high current mode occurs when starting the planar disks of the storage device from rest, which results in stopping the plurality of power supplies from operating in the redundant power supply configuration to the storage device such that the power supplies are no longer redundant and do not serve as backups to one another;
wherein operating the plurality of power supplies to supply the high current at the high current mode occurs when demand for the storage device is high, which results in stopping the plurality of power supplies from operating in the redundant power supply configuration to the storage device such that the power supplies are no longer redundant and do not serve as backups to one another; and
wherein operating the plurality of power supplies at the normal mode to provide the normal current causes the plurality of power supplies to again start operating in the redundant power supply configuration.
12. The power system of claim 11, wherein the power manager is configured to calculate the high current at the high current mode for each of the power supplies by:
obtaining a maximum current rating for each of the power supplies;
causing the total of the individual current for each of the power supplies to equally sum to the high current at the high current mode without exceeding the maximum current rating in high efficiency range for any one of the power supplies.
13. The power system of claim 11, wherein the power manager is configured to calculate the high current at the high current mode for each of the power supplies by:
obtaining present current outputs for each of the power supplies;
dividing the high current by a number of the power supplies to determine the individual current for each of the power supplies; and
causing each of the power supplies to individually increase present current outputs to the individual current respectively, such that the total of the individual current provides the high current at the high current mode.
14. The power system of claim 11, wherein the power manager is configured to execute the high current mode such that each of the power supplies operates at its respective maximum current.
15. The power system of claim 11, wherein in the normal mode the power manager is configured to individually operate each of the power supplies in a region of one-third of maximum capacity; and
wherein in the high current mode the power manager is configured to individually operate each of the power supplies individually in a region of maximum capacity.
16. The power system of claim 11,
wherein when the power manager operates the power supplies at the high current mode, the high current mode is configured to cause a device receiving the high current to: spin-up faster from rest than in the normal mode, and boot-up faster than in the normal mode.
US12/821,226 2010-06-23 2010-06-23 Redundant power supply configuration for a data center Expired - Fee Related US8671287B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/821,226 US8671287B2 (en) 2010-06-23 2010-06-23 Redundant power supply configuration for a data center

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/821,226 US8671287B2 (en) 2010-06-23 2010-06-23 Redundant power supply configuration for a data center

Publications (2)

Publication Number Publication Date
US20110320796A1 US20110320796A1 (en) 2011-12-29
US8671287B2 true US8671287B2 (en) 2014-03-11

Family

ID=45353701

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/821,226 Expired - Fee Related US8671287B2 (en) 2010-06-23 2010-06-23 Redundant power supply configuration for a data center

Country Status (1)

Country Link
US (1) US8671287B2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8656228B2 (en) 2010-06-23 2014-02-18 International Business Machines Corporation Memory error isolation and recovery in a multiprocessor computer system
US8683108B2 (en) 2010-06-23 2014-03-25 International Business Machines Corporation Connected input/output hub management
US8615622B2 (en) 2010-06-23 2013-12-24 International Business Machines Corporation Non-standard I/O adapters in a standardized I/O architecture
US8417911B2 (en) 2010-06-23 2013-04-09 International Business Machines Corporation Associating input/output device requests with memory associated with a logical partition
US8645767B2 (en) 2010-06-23 2014-02-04 International Business Machines Corporation Scalable I/O adapter function level error detection, isolation, and reporting
US8416834B2 (en) 2010-06-23 2013-04-09 International Business Machines Corporation Spread spectrum wireless communication code for data center environments
US8645606B2 (en) 2010-06-23 2014-02-04 International Business Machines Corporation Upbound input/output expansion request and response processing in a PCIe architecture
US8918573B2 (en) 2010-06-23 2014-12-23 International Business Machines Corporation Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment
US8751836B1 (en) * 2011-12-28 2014-06-10 Datadirect Networks, Inc. Data storage system and method for monitoring and controlling the power budget in a drive enclosure housing data storage devices
US9312694B2 (en) * 2012-07-03 2016-04-12 Oracle International Corporation Autonomous power system with variable sources and loads and associated methods
US9075595B2 (en) 2012-08-30 2015-07-07 Dell Products L.P. Power excursion warning system
US20150061384A1 (en) * 2013-08-27 2015-03-05 Amazon Technologies, Inc. Shared Backup Power For Data Centers
CN106292965B (en) * 2015-05-11 2019-02-12 光宝电子(广州)有限公司 Power system and its method of power supply supply

Citations (232)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104539A (en) * 1976-04-05 1978-08-01 Hase A M Parallel redundant and load sharing regulated AC system
US4611319A (en) * 1982-10-15 1986-09-09 Pioneer Electronic Corporation Disc drive control system
US4644443A (en) 1985-09-27 1987-02-17 Texas Instruments Incorporated Computer cooling system using recycled coolant
US5027254A (en) 1989-11-09 1991-06-25 International Business Machines Corporation Apparatus for cooling electronics components
US5170472A (en) 1991-03-28 1992-12-08 International Business Machines Corp. Dynamically changing a system i/o configuration definition
US5282274A (en) 1990-05-24 1994-01-25 International Business Machines Corporation Translation of multiple virtual pages upon a TLB miss
US5430856A (en) 1991-12-12 1995-07-04 Nec Corporation Data processing system simultaneously performing plural translations of virtual addresses having different page sizes
US5438575A (en) 1992-11-16 1995-08-01 Ampex Corporation Data storage system with stale data detector and method of operation
US5465355A (en) 1991-09-04 1995-11-07 International Business Machines Corporation Establishing and restoring paths in a data processing I/O system
US5465332A (en) 1992-09-21 1995-11-07 International Business Machines Corporation Selectable 8/16 bit DMA channels for "ISA" bus
US5535352A (en) 1994-03-24 1996-07-09 Hewlett-Packard Company Access hints for input/output address translation mechanisms
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5568365A (en) 1994-05-11 1996-10-22 Asian Micro Sources, Inc. High output, compact power supply
US5574873A (en) 1993-05-07 1996-11-12 Apple Computer, Inc. Decoding guest instruction to directly access emulation routines that emulate the guest instructions
US5600805A (en) 1992-06-15 1997-02-04 International Business Machines Corporation Pass-through for I/O channel subsystem call instructions for accessing shared resources in a computer system having a plurality of operating systems
US5617554A (en) 1992-02-10 1997-04-01 Intel Corporation Physical address size selection and page size selection in an address translator
US5663919A (en) * 1996-02-28 1997-09-02 Micron Technology, Inc. Memory device with regulated power supply control
US5742785A (en) 1992-12-18 1998-04-21 International Business Machines Corporation Posting multiple reservations with a conditional store atomic operations in a multiprocessing environment
US5761448A (en) 1996-08-30 1998-06-02 Ncr Corporation Physical-to-logical bus mapping scheme for computer systems having multiple PCI bus configuration
US5790825A (en) 1995-11-08 1998-08-04 Apple Computer, Inc. Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions
US5838960A (en) 1996-09-26 1998-11-17 Bay Networks, Inc. Apparatus for performing an atomic add instructions
US5870598A (en) 1994-09-20 1999-02-09 Intel Corporation Method and apparatus for providing an optimized compare-and-branch instruction
US5949646A (en) 1998-07-31 1999-09-07 Sun Microsystems, Inc. Compact computer having a redundant air moving system and method thereof
US5960213A (en) 1995-12-18 1999-09-28 3D Labs Inc. Ltd Dynamically reconfigurable multi-function PCI adapter device
US5963425A (en) 1997-07-16 1999-10-05 International Business Machines Corporation Combined air and refrigeration cooling for computer systems
US6009261A (en) 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6023736A (en) 1997-12-19 2000-02-08 International Business Machines Corporation System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter
US6067595A (en) 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
US6112311A (en) 1998-02-20 2000-08-29 International Business Machines Corporation Bridge failover system
US6205530B1 (en) 1997-05-08 2001-03-20 Hyundai Electronics Industries Co., Ltd. Address translation unit supporting variable page sizes
US6233693B1 (en) 1998-05-06 2001-05-15 International Business Machines Corporation Smart DASD spin-up
US6301133B1 (en) * 1999-04-07 2001-10-09 Astec International Limited Power supply system with ORing element and control circuit
US6308255B1 (en) 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US6330656B1 (en) 1999-03-31 2001-12-11 International Business Machines Corporation PCI slot control apparatus with dynamic configuration for partitioned systems
US6341064B1 (en) 2000-03-31 2002-01-22 Alcatel Usa Sourcing, L.P. Method and apparatus for thermal management in a telecommunications equipment cabinet
US6349380B1 (en) 1999-03-12 2002-02-19 Intel Corporation Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
US6362942B2 (en) 1999-03-19 2002-03-26 Ati International Srl Input stage protection circuit for a receiver
US6408347B1 (en) 1998-12-10 2002-06-18 Cisco Technology, Inc. Integrated multi-function adapters using standard interfaces through single a access point
US20020112067A1 (en) 2000-12-15 2002-08-15 International Business Machines Corporation Method and system for network management with per-endpoint adaptive data communication based on application life cycle
US6456498B1 (en) 2001-08-07 2002-09-24 Hewlett-Packard Co. CompactPCI-based computer system with mid-plane connector for equivalent front and back loading
US6523140B1 (en) 1999-10-07 2003-02-18 International Business Machines Corporation Computer system error recovery and fault isolation
US20030056155A1 (en) 2001-09-20 2003-03-20 International Business Machines Corporation Method and apparatus for filtering error logs in a logically partitioned data processing system
US6538881B1 (en) 2000-06-12 2003-03-25 Alcatel Canada Inc. Cooling of electronic equipment
US20030058618A1 (en) 2001-09-27 2003-03-27 Joseph Soetemans Method and apparatus for providing a common support services infrastructure for a network element
US6544311B1 (en) 2002-04-17 2003-04-08 Ag Communication Systems Corporation Chassis thermal zones
US20030097503A1 (en) 2001-11-19 2003-05-22 Huckins Jeffrey L. PCI compatible bus model for non-PCI compatible bus architectures
US6594148B1 (en) 2002-01-16 2003-07-15 Cisco Technology, Inc. Airflow system
US6595018B2 (en) 2001-06-29 2003-07-22 International Business Machines Corporation Logic module refrigeration system with condensation control
US20030177221A1 (en) 2002-03-18 2003-09-18 Hamid Ould-Brahim Resource allocation using an auto-discovery mechanism for provider-provisioned layer-2 and layer-3 Virtual Private Networks
US6625648B1 (en) 2000-01-07 2003-09-23 Netiq Corporation Methods, systems and computer program products for network performance testing through active endpoint pair based testing and passive application monitoring
US6625169B1 (en) 2002-06-14 2003-09-23 Telesys Technologies, Inc. Integrated communication systems for exchanging data and information between networks
US20030200477A1 (en) 2002-04-17 2003-10-23 International Business Machines Corporation Method, system, and program for selecting a path to a device to use when sending data requests to the device
US20030198180A1 (en) 2002-04-10 2003-10-23 Keith Cambron Route on failure method and apparatus for automatic rerouting network traffic through a reconfigurable, intelligent signal multiplexer upon failures of multiplexer components or of network spans
US6643727B1 (en) 2000-06-08 2003-11-04 International Business Machines Corporation Isolation of I/O bus errors to a single partition in an LPAR environment
US6658599B1 (en) 2000-06-22 2003-12-02 International Business Machines Corporation Method for recovering from a machine check interrupt during runtime
US20040024905A1 (en) 2002-07-30 2004-02-05 Brocade Communications Systems, Inc. Method and apparatus for transparent communication between a fibre channel network and an infiniband network
US6721813B2 (en) 2001-01-30 2004-04-13 Advanced Micro Devices, Inc. Computer system implementing a system and method for tracking the progress of posted write transactions
US20040117534A1 (en) 2002-12-13 2004-06-17 Parry Owen N. Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system
US20040133819A1 (en) 2002-10-24 2004-07-08 Sun Microsystems, Inc. System and method for providing a persistent power mask
US20040130868A1 (en) 2003-01-08 2004-07-08 Schwartz William H. Cooling system including redundant fan controllers
US20040136130A1 (en) 2003-01-13 2004-07-15 Xerox Corporation High voltage level translator
US20040199700A1 (en) 2003-04-03 2004-10-07 Clayton Shawn Adam Virtual peripheral component interconnect multiple-function device
US6816590B2 (en) 2001-09-27 2004-11-09 Alcatel Canada Inc. System and method of configuring a network element
US6845428B1 (en) 1998-01-07 2005-01-18 Emc Corporation Method and apparatus for managing the dynamic assignment of resources in a data storage system
US20050024187A1 (en) * 2003-07-28 2005-02-03 Kranz Mark J. System and method for optimizing power usage in a radio frequency communication device
US20050033895A1 (en) 2003-08-09 2005-02-10 Lueck Andrew W. System for signaling serialized interrupts using message signaled interrupts
US20050071472A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and system for hardware enforcement of logical partitioning of a channel adapter's resources in a system area network
US20050091438A1 (en) 2003-10-24 2005-04-28 Sun Microsystems, Inc. Exporting 12C controller interfaces for 12C slave devices using IPMI micro-controller
US20050116546A1 (en) * 2003-12-02 2005-06-02 Zeighami Roy M. Power supply system
US20050146855A1 (en) 2004-01-07 2005-07-07 International Business Machines Corporation System and method for aligning and supporting interconnect systems
US20050160214A1 (en) 2004-01-15 2005-07-21 Dell Products L.P. Information handling system capable of operating with multiple types of expansion cards in a common industry standard connector
US20050162830A1 (en) 2004-01-27 2005-07-28 Hewlett-Packard Development Company, L.P. Electronic system with a simplified enclosure
US6927975B2 (en) 2003-06-27 2005-08-09 International Business Machines Corporation Server blade modular chassis mechanical and thermal design
US20050182862A1 (en) 2004-02-12 2005-08-18 Ritz Andrew J. System and method for detecting DMA-generated memory corruption in a PCI express bus system
US6950438B1 (en) 1999-09-17 2005-09-27 Advanced Micro Devices, Inc. System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system
US20050213513A1 (en) 2004-03-25 2005-09-29 Alcatel Full mesh LSP and full mesh T-LDP provisioning between provider edge routers in support of Layer-2 and Layer-3 Virtual Private Network services
US6973510B2 (en) 2000-06-08 2005-12-06 International Business Machines Corporation DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge
US20050276017A1 (en) 2004-06-10 2005-12-15 Farid Aziz Common plenum and air intake airflow management for telecom equipment
US20050289278A1 (en) 2004-06-24 2005-12-29 Tan Thian A Apparatus and method for programmable completion tracking logic to support multiple virtual channels
US20050286187A1 (en) 2004-06-24 2005-12-29 Jeng-Shu Liu Esd preventing-able level shifters
US20050289271A1 (en) 2004-06-29 2005-12-29 Martinez Alberto J Circuitry to selectively produce MSI signals
US7003615B2 (en) 2002-04-22 2006-02-21 Broadcom Corporation Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device
US7004233B2 (en) 2001-10-05 2006-02-28 Honda Giken Kogyo Kabushiki Kaisha Cooling structure for high tension electrical equipment
US7007099B1 (en) 1999-05-03 2006-02-28 Lucent Technologies Inc. High speed multi-port serial-to-PCI bus interface
US20060053339A1 (en) 2002-05-31 2006-03-09 Microsoft Corporation Virtual logging system and method
US20060067069A1 (en) 2004-09-30 2006-03-30 Christopher Heard Electronic system with non-parallel arrays of circuit card assemblies
US20060085150A1 (en) 2004-10-18 2006-04-20 Gorin Joseph M Phase noise compensation for phase noise measurements
US20060085573A1 (en) 2004-10-15 2006-04-20 Dell Products L.P. Multi-context selection with PCI express to support hardware partitioning
US20060087813A1 (en) 2004-10-25 2006-04-27 International Business Machines Corporation System for airflow management in electronic enclosures
US20060087814A1 (en) 2004-10-25 2006-04-27 International Business Machines Corporation System for airflow management in electronic enclosures
US20060095607A1 (en) 2004-10-29 2006-05-04 Lim Su W PCI to PCI express protocol conversion
US7042734B2 (en) 2003-01-23 2006-05-09 Hewlett-Packard Development Company, L.P. Multi-slot CompactPCI blade assembly
US7053502B2 (en) * 1998-12-25 2006-05-30 Hitachi, Ltd. Power supply with uninterruptible function
US7062594B1 (en) 2004-06-30 2006-06-13 Emc Corporation Root complex connection system
US7075788B2 (en) 2003-06-11 2006-07-11 Hewlett-Packard Development Company, L.P. Computer cooling system and method
US7093155B2 (en) 2003-11-18 2006-08-15 Hitachi, Ltd. Information processing system and method for path failover
US7096308B2 (en) 2003-08-29 2006-08-22 Texas Instruments Incorporated LPC transaction bridging across a PCI—express docking connection
US20060195644A1 (en) 2005-02-25 2006-08-31 International Business Machines Corporation Interrupt mechanism on an IO adapter that supports virtualization
US7107495B2 (en) 2003-06-19 2006-09-12 International Business Machines Corporation Method, system, and product for improving isolation of input/output errors in logically partitioned data processing systems
US7107331B2 (en) 2002-03-25 2006-09-12 Kabushiki Kaisha Toshiba System and method for configuring digital image devices
US20060206639A1 (en) 2005-03-14 2006-09-14 Phison Electronics Corp. [virtual ide card reader with pci express]
US20060230208A1 (en) 2005-04-07 2006-10-12 Gregg Thomas A System and method for presenting interrupts
US20060236054A1 (en) 2005-04-19 2006-10-19 Manabu Kitamura Highly available external storage system
US20060237636A1 (en) * 2003-06-23 2006-10-26 Advanced Optical Technologies, Llc Integrating chamber LED lighting with pulse amplitude modulation to set color and/or intensity of output
US20060253619A1 (en) 2005-04-22 2006-11-09 Ola Torudbakken Virtualization for device sharing
US7152136B1 (en) 2004-08-03 2006-12-19 Altera Corporation Implementation of PCI express
US20060288130A1 (en) 2005-06-21 2006-12-21 Rajesh Madukkarumukumana Address window support for direct memory access translation
US20060291447A1 (en) 2003-07-29 2006-12-28 John Siliquini Virtual circuits in packet networks
US20070008663A1 (en) 2005-07-08 2007-01-11 Fujitsu Limited Electronic apparatus having DC voltage conversion function, and DC voltage converter
US7163546B2 (en) 2001-12-21 2007-01-16 Mirizzi Michael S Method and apparatus for avulsion of varicose veins
US20070073955A1 (en) 2005-09-29 2007-03-29 Joseph Murray Multi-function PCI device
US20070069585A1 (en) 2005-09-29 2007-03-29 International Business Machines Corporation Fail safe redundant power supply in a multi-node computer system
US20070078996A1 (en) 2005-10-04 2007-04-05 Wei-Che Chen Method for managing a network appliance and transparent configurable network appliance
US7206946B2 (en) 2003-10-09 2007-04-17 Hitachi, Ltd. Disk drive system for starting destaging of unwritten cache memory data to disk drive upon detection of DC voltage level falling below predetermined value
US7219181B2 (en) 2005-02-03 2007-05-15 Cisco Technology, Inc. Dual use modular PCI/PCI express interface
US20070136554A1 (en) 2005-12-12 2007-06-14 Giora Biran Memory operations in a virtualized system
US20070168636A1 (en) 2006-01-17 2007-07-19 Hummel Mark D Chained Hybrid IOMMU
US20070183393A1 (en) 2006-02-07 2007-08-09 Boyd William T Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system
US20070186074A1 (en) 2005-01-14 2007-08-09 Bradford Jeffrey P Multiple page size address translation incorporating page size prediction
US7260620B1 (en) 2000-01-05 2007-08-21 Cisco Technology, Inc. System for selecting the operating frequency of a communication device in a wireless network
US20070211430A1 (en) 2006-01-13 2007-09-13 Sun Microsystems, Inc. Compact rackmount server
US20070226523A1 (en) * 2006-03-23 2007-09-27 Inventec Corporation System for controlling sequential startup of hard disks
US20070226386A1 (en) 2006-02-17 2007-09-27 Neteffect, Inc. Method and apparatus for using a single multi-function adapter with different operating systems
US20070239925A1 (en) 2006-04-11 2007-10-11 Nec Corporation PCI express link, multi host computer system, and method of reconfiguring PCI express link
US20070245041A1 (en) 2006-03-21 2007-10-18 Binh Hua Method to improve system DMA mapping while substantially reducing memory fragmentation
US20070262891A1 (en) 2005-09-09 2007-11-15 Woodral David E Method and system for synchronizing bit streams for pci express devices
US20070271559A1 (en) 2006-05-17 2007-11-22 International Business Machines Corporation Virtualization of infiniband host channel adapter interruptions
US20070273018A1 (en) 2006-03-29 2007-11-29 Kabushiki Kaisha Toshiba Semiconductor apparatus and method for manufacturing the same
US20070274039A1 (en) 2006-05-25 2007-11-29 Motorola, Inc. Embedded computer chassis with redundant fan trays
US20070273401A1 (en) 2006-04-20 2007-11-29 Naoki Kiryu Systems and Methods for Improved Fault Coverage of LBIST Testing
US7313643B2 (en) 2004-02-17 2007-12-25 Nec Electronics America, Inc. PCI-express to PCI/PCI X translator
US20080043405A1 (en) 2006-08-16 2008-02-21 Tyan Computer Corporation Chassis partition architecture for multi-processor system
US20080065796A1 (en) 1999-08-04 2008-03-13 Super Talent Electronics Inc. High-Level Bridge From PCIE to Extended USB
US20080069141A1 (en) 2006-09-20 2008-03-20 Reuters America Inc. Messaging model and architecture
US20080077817A1 (en) * 2006-09-26 2008-03-27 Dell Products L.P. Apparatus and Methods for Managing Power in an Information Handling System
US20080091915A1 (en) 2006-10-17 2008-04-17 Moertl Daniel F Apparatus and Method for Communicating with a Memory Registration Enabled Adapter Using Cached Address Translations
US20080091851A1 (en) 2006-10-10 2008-04-17 Palm, Inc. System and method for dynamic audio buffer management
US20080091868A1 (en) 2006-10-17 2008-04-17 Shay Mizrachi Method and System for Delayed Completion Coalescing
US7370224B1 (en) 2005-02-17 2008-05-06 Alcatel Usa Sourcing, Inc System and method for enabling redundancy in PCI-Express architecture
US20080114906A1 (en) 2006-11-13 2008-05-15 Hummel Mark D Efficiently Controlling Special Memory Mapped System Accesses
US20080126652A1 (en) 2006-09-27 2008-05-29 Intel Corporation Managing Interrupts in a Partitioned Platform
US20080126648A1 (en) 2006-08-28 2008-05-29 Sean Thomas Brownlow Message Signaled Interrupt Management for a Computer Input/Output Fabric Incorporating Platform Independent Interrupt Manager
US20080147943A1 (en) 2006-12-19 2008-06-19 Douglas M Freimuth System and method for migration of a virtual endpoint from one virtual plane to another
US20080148295A1 (en) 2006-12-19 2008-06-19 Freimuth Douglas M System and method for migration of single root stateless virtual functions
US20080162865A1 (en) 2006-12-29 2008-07-03 Koufaty David A Partitioning memory mapped device configuration space
US20080168208A1 (en) 2007-01-09 2008-07-10 International Business Machines Corporation I/O Adapter LPAR Isolation In A Hypertransport Environment With Assigned Memory Space Indexing a TVT Via Unit IDs
US20080189577A1 (en) 2004-07-08 2008-08-07 International Business Machines Corporation Isolation of Input/Output Adapter Error Domains
US20080192431A1 (en) 2006-01-13 2008-08-14 Sun Microsystems, Inc. Compact rackmount server
US20080209114A1 (en) 1999-08-04 2008-08-28 Super Talent Electronics, Inc. Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System
US20080222406A1 (en) 2007-03-06 2008-09-11 Nec Corporation Hot-pluggable information processing device and setting method
US20080235425A1 (en) 2003-05-12 2008-09-25 International Business Machines Corporation Managing input/output interruptions in non-dedicated interruption hardware environments
US20080239687A1 (en) 2007-03-29 2008-10-02 Leigh Kevin B Server infrastructure having independent backplanes to distribute power and to route signals
US20080239945A1 (en) 2007-03-30 2008-10-02 International Business Machines Corporation Peripheral component switch having automatic link failover
US20080263246A1 (en) 2007-04-17 2008-10-23 Larson Chad J System and Method for Balancing PCI-Express Bandwidth
US20080259555A1 (en) 2006-01-13 2008-10-23 Sun Microsystems, Inc. Modular blade server
US20080270853A1 (en) 2005-10-27 2008-10-30 International Business Machines Corporation Method of Routing I/O Adapter Error Messages in a Multi-Host Environment
US20080288661A1 (en) 2007-05-16 2008-11-20 Michael Galles Method and system to map virtual i/o devices and resources to a standard i/o bus
US7457900B2 (en) 2006-06-20 2008-11-25 Intel Corporation Method for discovering and partitioning PCI devices
US7464174B1 (en) 2005-03-07 2008-12-09 Pericom Semiconductor Corp. Shared network-interface controller (NIC) using advanced switching (AS) turn-pool routing field to select from among multiple contexts for multiple processors
US7480303B1 (en) 2005-05-16 2009-01-20 Pericom Semiconductor Corp. Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports
US20090037682A1 (en) 2007-08-02 2009-02-05 International Business Machines Corporation Hypervisor-enforced isolation of entities within a single logical partition's virtual address space
WO2009027189A1 (en) 2007-08-29 2009-03-05 International Business Machines Corporation Autonomic pci express hardware detection and failover mechanism
US20090070760A1 (en) 2007-09-06 2009-03-12 Mukund Khatri Virtual Machine (VM) Migration Between Processor Architectures
US7519647B2 (en) 2005-02-09 2009-04-14 International Business Machines Corporation System and method for providing a decimal multiply algorithm using a double adder
US7525957B2 (en) 2005-09-01 2009-04-28 Emulex Design & Manufacturing Corporation Input/output router for storage networks
US20090125666A1 (en) 2006-08-22 2009-05-14 International Business Machines Corporation Dynamically scalable queues for performance driven pci express memory traffic
US7535828B2 (en) 2005-03-18 2009-05-19 Cisco Technology, Inc. Algorithm for backup PE selection
US20090144731A1 (en) 2007-12-03 2009-06-04 Brown Aaron C System and method for distribution of resources for an i/o virtualized (iov) adapter and management of the adapter through an iov management partition
US20090144462A1 (en) 2005-02-28 2009-06-04 International Business Machines Corporation Method and System for Fully Trusted Adapter Validation of Addresses Referenced in a Virtual Host Transfer Request
US7546386B2 (en) 2005-02-25 2009-06-09 International Business Machines Corporation Method for virtual resource initialization on a physical adapter that supports virtual resources
US7558348B1 (en) 2005-01-24 2009-07-07 Nvidia Corporation Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications
US20090182969A1 (en) 2008-01-16 2009-07-16 Steven Paul Norgaard Dynamic allocation of dma buffers in input/output adaptors
US20090182966A1 (en) 2008-01-11 2009-07-16 International Business Machines Corporation Dynamic address translation with frame management
US7565463B2 (en) 2005-04-22 2009-07-21 Sun Microsystems, Inc. Scalable routing and addressing
US20090210646A1 (en) 2008-02-14 2009-08-20 Bauman Ellen M Cross Adapter Shared Address Translation Tables
US20090210527A1 (en) 2006-05-24 2009-08-20 Masahiro Kawato Virtual Machine Management Apparatus, and Virtual Machine Management Method and Program
US20090222814A1 (en) 2008-02-28 2009-09-03 Sony Ericsson Mobile Communications Ab Selective exposure to usb device functionality for a virtual machine
US20090234987A1 (en) 2008-03-12 2009-09-17 Mips Technologies, Inc. Efficient, Scalable and High Performance Mechanism for Handling IO Requests
US7594144B2 (en) 2006-08-14 2009-09-22 International Business Machines Corporation Handling fatal computer hardware errors
US20090240849A1 (en) 2006-08-01 2009-09-24 International Business Machines Corporation System and Method for Distributing Virtual Input/Output Operations Across Multiple Logical Partitions
US20090249039A1 (en) 1997-10-09 2009-10-01 Mips Technologies, Inc. Providing Extended Precision in SIMD Vector Arithmetic Operations
US7613847B2 (en) 2006-05-16 2009-11-03 Hewlett-Packard Development Company, L.P. Partially virtualizing an I/O device for use by virtual machines
US20090276773A1 (en) 2008-05-05 2009-11-05 International Business Machines Corporation Multi-Root I/O Virtualization Using Separate Management Facilities of Multiple Logical Partitions
US20090276774A1 (en) 2008-05-01 2009-11-05 Junji Kinoshita Access control for virtual machines in an information system
US20090276551A1 (en) 2008-05-05 2009-11-05 International Business Machines Corporation Native and Non-Native I/O Virtualization in a Single Adapter
US7617340B2 (en) 2007-01-09 2009-11-10 International Business Machines Corporation I/O adapter LPAR isolation with assigned memory space
US7617345B2 (en) 2007-07-02 2009-11-10 International Business Machines Corporation Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
US7624235B2 (en) 2006-11-30 2009-11-24 Apple Inc. Cache used both as cache and staging buffer
US7627723B1 (en) 2006-09-21 2009-12-01 Nvidia Corporation Atomic memory operators in a parallel processor
US7631097B2 (en) 2005-07-21 2009-12-08 National Instruments Corporation Method and apparatus for optimizing the responsiveness and throughput of a system performing packetized data transfers using a transfer count mark
US20090328035A1 (en) 2008-06-27 2009-12-31 Microsoft Corporation Lazy Handling of End of Interrupt Messages in a Virtualized Environment
US20100005234A1 (en) 2008-06-30 2010-01-07 Ganga Ilango S Enabling functional dependency in a multi-function device
US20100005531A1 (en) 2004-12-23 2010-01-07 Kenneth Largman Isolated multiplexed multi-dimensional processing in a virtual processing space having virus, spyware, and hacker protection features
US20100027559A1 (en) 2008-07-31 2010-02-04 Hung-Ming Lin Transmission device and data extended transmission method
US7660912B2 (en) 2006-10-18 2010-02-09 International Business Machines Corporation I/O adapter LPAR isolation in a hypertransport environment
US20100042999A1 (en) 2008-08-15 2010-02-18 International Business Machines Corporation Transactional quality of service in event stream processing middleware
US7676617B2 (en) 2008-03-31 2010-03-09 Lsi Corporation Posted memory write verification
US20100077117A1 (en) 2008-09-22 2010-03-25 Micron Technology, Inc. SATA MASS STORAGE DEVICE EMULATION ON A PCIe INTERFACE
US20100115329A1 (en) 2008-10-30 2010-05-06 Hitachi, Ltd. Storage Device, and Data path Failover Method of Internal Network of Storage Controller
US20100131359A1 (en) 2008-11-26 2010-05-27 Yahoo! Inc. System and method for securing invocations for serving advertisements and instrumentation in online advertising
US7729316B2 (en) 2002-09-30 2010-06-01 Intel Corporation Receiving signals on a channel used for traffic and access in a communications system
US20100146089A1 (en) 2008-12-09 2010-06-10 International Business Machines Corporation Use of Peripheral Component Interconnect Input/Output Virtualization Devices to Create High-Speed, Low-Latency Interconnect
US20100157463A1 (en) * 2008-12-18 2010-06-24 Arizono Yukiko Disk drive spin control
US20100169674A1 (en) * 2008-09-26 2010-07-01 Fujitsu Limited Power-source control system and power-source control method
US20100205608A1 (en) 2001-09-28 2010-08-12 Nemirovsky Mario D Mechanism for Managing Resource Locking in a Multi-Threaded Environment
US20100211714A1 (en) 2009-02-13 2010-08-19 Unisys Corporation Method, system, and apparatus for transferring data between system memory and input/output busses
US20100287209A1 (en) 2009-05-05 2010-11-11 Paul A. Lipari System, method and computer readable medium for binding authored content to the events used to generate the content
US7836254B2 (en) 2007-12-18 2010-11-16 International Business Machines Corporation Cache injection using speculation
US20100312894A1 (en) 2008-02-05 2010-12-09 Nec Corporation Resource allocation
US7873851B1 (en) * 2007-09-28 2011-01-18 Emc Corporation Powering disk drive spinup
US20110029696A1 (en) 2009-07-28 2011-02-03 Oki Semiconductor Co., Ltd. Information processing device
US20110029734A1 (en) 2009-07-29 2011-02-03 Solarflare Communications Inc Controller Integration
US20110131359A1 (en) 2006-02-28 2011-06-02 Emulex Design And Manufacturing Corporation Programmable bridge header structures
US7975076B2 (en) 2003-01-14 2011-07-05 Hitachi, Ltd. Data processing system for keeping isolation between logical partitions
US20110219161A1 (en) 2008-03-26 2011-09-08 Lsi Corporation System and method for providing address decode and virtual function (vf) migration support in a peripheral component interconnect express (pcie) multi-root input/output virtualization (iov) environment
US8041811B2 (en) 2009-04-21 2011-10-18 Alcatel Lucent Multi-chassis component corrector and associator engine
US20110258352A1 (en) 2010-04-20 2011-10-20 Emulex Design & Manufacturing Corporation Inline PCI-IOV Adapter
US8046627B2 (en) 2008-12-05 2011-10-25 Hitachi, Ltd. Server failover control method and apparatus and computer system group
US20110265134A1 (en) 2009-11-04 2011-10-27 Pawan Jaggi Switchable multi-channel data transcoding and transrating system
US20110320602A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Discovery of logical images at storage area network endpoints
US20110320892A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Memory error isolation and recovery in a multiprocessor computer system
US20110320674A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Upbound input/output expansion request and response processing in a pcie architecture
US20110320861A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Switch failover control in a multiprocessor computer system
US20110317743A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Spread spectrum wireless communication code for data center environments
US20110317351A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Server drawer
US20110320675A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation SYSTEM AND METHOD FOR DOWNBOUND I/O EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIe ARCHITECTURE
US20110320703A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Associating input/output device requests with memory associated with a logical partition
US20110320670A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Connected input/output hub management
US20110320666A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Input/output (i/o) expansion response processing in a peripheral component interconnect express (pcie) environment
US20110320887A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Scalable i/o adapter function level error detection, isolation, and reporting
US20110320653A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation System and method for routing i/o expansion requests and responses in a pcie architecture
US8140917B2 (en) 2009-03-13 2012-03-20 Hitachi, Ltd. Stream recovery method, stream recovery program and failure recovery apparatus

Patent Citations (237)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104539A (en) * 1976-04-05 1978-08-01 Hase A M Parallel redundant and load sharing regulated AC system
US4611319A (en) * 1982-10-15 1986-09-09 Pioneer Electronic Corporation Disc drive control system
US4644443A (en) 1985-09-27 1987-02-17 Texas Instruments Incorporated Computer cooling system using recycled coolant
US5027254A (en) 1989-11-09 1991-06-25 International Business Machines Corporation Apparatus for cooling electronics components
US5282274A (en) 1990-05-24 1994-01-25 International Business Machines Corporation Translation of multiple virtual pages upon a TLB miss
US5170472A (en) 1991-03-28 1992-12-08 International Business Machines Corp. Dynamically changing a system i/o configuration definition
US5465355A (en) 1991-09-04 1995-11-07 International Business Machines Corporation Establishing and restoring paths in a data processing I/O system
US5430856A (en) 1991-12-12 1995-07-04 Nec Corporation Data processing system simultaneously performing plural translations of virtual addresses having different page sizes
US5617554A (en) 1992-02-10 1997-04-01 Intel Corporation Physical address size selection and page size selection in an address translator
US5600805A (en) 1992-06-15 1997-02-04 International Business Machines Corporation Pass-through for I/O channel subsystem call instructions for accessing shared resources in a computer system having a plurality of operating systems
US5465332A (en) 1992-09-21 1995-11-07 International Business Machines Corporation Selectable 8/16 bit DMA channels for "ISA" bus
US5438575A (en) 1992-11-16 1995-08-01 Ampex Corporation Data storage system with stale data detector and method of operation
US5742785A (en) 1992-12-18 1998-04-21 International Business Machines Corporation Posting multiple reservations with a conditional store atomic operations in a multiprocessing environment
US5574873A (en) 1993-05-07 1996-11-12 Apple Computer, Inc. Decoding guest instruction to directly access emulation routines that emulate the guest instructions
US5535352A (en) 1994-03-24 1996-07-09 Hewlett-Packard Company Access hints for input/output address translation mechanisms
US5568365A (en) 1994-05-11 1996-10-22 Asian Micro Sources, Inc. High output, compact power supply
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5870598A (en) 1994-09-20 1999-02-09 Intel Corporation Method and apparatus for providing an optimized compare-and-branch instruction
US5790825A (en) 1995-11-08 1998-08-04 Apple Computer, Inc. Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions
US5960213A (en) 1995-12-18 1999-09-28 3D Labs Inc. Ltd Dynamically reconfigurable multi-function PCI adapter device
US5663919A (en) * 1996-02-28 1997-09-02 Micron Technology, Inc. Memory device with regulated power supply control
US5761448A (en) 1996-08-30 1998-06-02 Ncr Corporation Physical-to-logical bus mapping scheme for computer systems having multiple PCI bus configuration
US5838960A (en) 1996-09-26 1998-11-17 Bay Networks, Inc. Apparatus for performing an atomic add instructions
US6205530B1 (en) 1997-05-08 2001-03-20 Hyundai Electronics Industries Co., Ltd. Address translation unit supporting variable page sizes
US5963425A (en) 1997-07-16 1999-10-05 International Business Machines Corporation Combined air and refrigeration cooling for computer systems
US6067595A (en) 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
US20090249039A1 (en) 1997-10-09 2009-10-01 Mips Technologies, Inc. Providing Extended Precision in SIMD Vector Arithmetic Operations
US6009261A (en) 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6023736A (en) 1997-12-19 2000-02-08 International Business Machines Corporation System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter
US6845428B1 (en) 1998-01-07 2005-01-18 Emc Corporation Method and apparatus for managing the dynamic assignment of resources in a data storage system
US6112311A (en) 1998-02-20 2000-08-29 International Business Machines Corporation Bridge failover system
US6233693B1 (en) 1998-05-06 2001-05-15 International Business Machines Corporation Smart DASD spin-up
US6308255B1 (en) 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US5949646A (en) 1998-07-31 1999-09-07 Sun Microsystems, Inc. Compact computer having a redundant air moving system and method thereof
US6408347B1 (en) 1998-12-10 2002-06-18 Cisco Technology, Inc. Integrated multi-function adapters using standard interfaces through single a access point
US7053502B2 (en) * 1998-12-25 2006-05-30 Hitachi, Ltd. Power supply with uninterruptible function
US6349380B1 (en) 1999-03-12 2002-02-19 Intel Corporation Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
US6362942B2 (en) 1999-03-19 2002-03-26 Ati International Srl Input stage protection circuit for a receiver
US6330656B1 (en) 1999-03-31 2001-12-11 International Business Machines Corporation PCI slot control apparatus with dynamic configuration for partitioned systems
US6301133B1 (en) * 1999-04-07 2001-10-09 Astec International Limited Power supply system with ORing element and control circuit
US7007099B1 (en) 1999-05-03 2006-02-28 Lucent Technologies Inc. High speed multi-port serial-to-PCI bus interface
US20080065796A1 (en) 1999-08-04 2008-03-13 Super Talent Electronics Inc. High-Level Bridge From PCIE to Extended USB
US20080209114A1 (en) 1999-08-04 2008-08-28 Super Talent Electronics, Inc. Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System
US6950438B1 (en) 1999-09-17 2005-09-27 Advanced Micro Devices, Inc. System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system
US6523140B1 (en) 1999-10-07 2003-02-18 International Business Machines Corporation Computer system error recovery and fault isolation
US7260620B1 (en) 2000-01-05 2007-08-21 Cisco Technology, Inc. System for selecting the operating frequency of a communication device in a wireless network
US6625648B1 (en) 2000-01-07 2003-09-23 Netiq Corporation Methods, systems and computer program products for network performance testing through active endpoint pair based testing and passive application monitoring
US6341064B1 (en) 2000-03-31 2002-01-22 Alcatel Usa Sourcing, L.P. Method and apparatus for thermal management in a telecommunications equipment cabinet
US6973510B2 (en) 2000-06-08 2005-12-06 International Business Machines Corporation DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge
US6643727B1 (en) 2000-06-08 2003-11-04 International Business Machines Corporation Isolation of I/O bus errors to a single partition in an LPAR environment
US6538881B1 (en) 2000-06-12 2003-03-25 Alcatel Canada Inc. Cooling of electronic equipment
US6658599B1 (en) 2000-06-22 2003-12-02 International Business Machines Corporation Method for recovering from a machine check interrupt during runtime
US20020112067A1 (en) 2000-12-15 2002-08-15 International Business Machines Corporation Method and system for network management with per-endpoint adaptive data communication based on application life cycle
US6721813B2 (en) 2001-01-30 2004-04-13 Advanced Micro Devices, Inc. Computer system implementing a system and method for tracking the progress of posted write transactions
US6595018B2 (en) 2001-06-29 2003-07-22 International Business Machines Corporation Logic module refrigeration system with condensation control
US6456498B1 (en) 2001-08-07 2002-09-24 Hewlett-Packard Co. CompactPCI-based computer system with mid-plane connector for equivalent front and back loading
US20030056155A1 (en) 2001-09-20 2003-03-20 International Business Machines Corporation Method and apparatus for filtering error logs in a logically partitioned data processing system
US20030058618A1 (en) 2001-09-27 2003-03-27 Joseph Soetemans Method and apparatus for providing a common support services infrastructure for a network element
US6816590B2 (en) 2001-09-27 2004-11-09 Alcatel Canada Inc. System and method of configuring a network element
US20100205608A1 (en) 2001-09-28 2010-08-12 Nemirovsky Mario D Mechanism for Managing Resource Locking in a Multi-Threaded Environment
US7004233B2 (en) 2001-10-05 2006-02-28 Honda Giken Kogyo Kabushiki Kaisha Cooling structure for high tension electrical equipment
US20030097503A1 (en) 2001-11-19 2003-05-22 Huckins Jeffrey L. PCI compatible bus model for non-PCI compatible bus architectures
US7163546B2 (en) 2001-12-21 2007-01-16 Mirizzi Michael S Method and apparatus for avulsion of varicose veins
US6594148B1 (en) 2002-01-16 2003-07-15 Cisco Technology, Inc. Airflow system
US7478167B2 (en) 2002-03-18 2009-01-13 Nortel Networks Limited Resource allocation using an auto-discovery mechanism for provider-provisioned layer-2 and layer-3 virtual private networks
US20030177221A1 (en) 2002-03-18 2003-09-18 Hamid Ould-Brahim Resource allocation using an auto-discovery mechanism for provider-provisioned layer-2 and layer-3 Virtual Private Networks
US7107331B2 (en) 2002-03-25 2006-09-12 Kabushiki Kaisha Toshiba System and method for configuring digital image devices
US20030198180A1 (en) 2002-04-10 2003-10-23 Keith Cambron Route on failure method and apparatus for automatic rerouting network traffic through a reconfigurable, intelligent signal multiplexer upon failures of multiplexer components or of network spans
US7134040B2 (en) 2002-04-17 2006-11-07 International Business Machines Corporation Method, system, and program for selecting a path to a device to use when sending data requests to the device
US6544311B1 (en) 2002-04-17 2003-04-08 Ag Communication Systems Corporation Chassis thermal zones
US20030200477A1 (en) 2002-04-17 2003-10-23 International Business Machines Corporation Method, system, and program for selecting a path to a device to use when sending data requests to the device
US7003615B2 (en) 2002-04-22 2006-02-21 Broadcom Corporation Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device
US20060053339A1 (en) 2002-05-31 2006-03-09 Microsoft Corporation Virtual logging system and method
US6625169B1 (en) 2002-06-14 2003-09-23 Telesys Technologies, Inc. Integrated communication systems for exchanging data and information between networks
US20040024905A1 (en) 2002-07-30 2004-02-05 Brocade Communications Systems, Inc. Method and apparatus for transparent communication between a fibre channel network and an infiniband network
US7729316B2 (en) 2002-09-30 2010-06-01 Intel Corporation Receiving signals on a channel used for traffic and access in a communications system
US20040133819A1 (en) 2002-10-24 2004-07-08 Sun Microsystems, Inc. System and method for providing a persistent power mask
US20040117534A1 (en) 2002-12-13 2004-06-17 Parry Owen N. Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system
US20040130868A1 (en) 2003-01-08 2004-07-08 Schwartz William H. Cooling system including redundant fan controllers
US20040136130A1 (en) 2003-01-13 2004-07-15 Xerox Corporation High voltage level translator
US7975076B2 (en) 2003-01-14 2011-07-05 Hitachi, Ltd. Data processing system for keeping isolation between logical partitions
US7042734B2 (en) 2003-01-23 2006-05-09 Hewlett-Packard Development Company, L.P. Multi-slot CompactPCI blade assembly
US20040199700A1 (en) 2003-04-03 2004-10-07 Clayton Shawn Adam Virtual peripheral component interconnect multiple-function device
US20080235425A1 (en) 2003-05-12 2008-09-25 International Business Machines Corporation Managing input/output interruptions in non-dedicated interruption hardware environments
US7075788B2 (en) 2003-06-11 2006-07-11 Hewlett-Packard Development Company, L.P. Computer cooling system and method
US7107495B2 (en) 2003-06-19 2006-09-12 International Business Machines Corporation Method, system, and product for improving isolation of input/output errors in logically partitioned data processing systems
US20060237636A1 (en) * 2003-06-23 2006-10-26 Advanced Optical Technologies, Llc Integrating chamber LED lighting with pulse amplitude modulation to set color and/or intensity of output
US6927975B2 (en) 2003-06-27 2005-08-09 International Business Machines Corporation Server blade modular chassis mechanical and thermal design
US20050024187A1 (en) * 2003-07-28 2005-02-03 Kranz Mark J. System and method for optimizing power usage in a radio frequency communication device
US20060291447A1 (en) 2003-07-29 2006-12-28 John Siliquini Virtual circuits in packet networks
US20050033895A1 (en) 2003-08-09 2005-02-10 Lueck Andrew W. System for signaling serialized interrupts using message signaled interrupts
US7096308B2 (en) 2003-08-29 2006-08-22 Texas Instruments Incorporated LPC transaction bridging across a PCI—express docking connection
US20050071472A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and system for hardware enforcement of logical partitioning of a channel adapter's resources in a system area network
US7206946B2 (en) 2003-10-09 2007-04-17 Hitachi, Ltd. Disk drive system for starting destaging of unwritten cache memory data to disk drive upon detection of DC voltage level falling below predetermined value
US20050091438A1 (en) 2003-10-24 2005-04-28 Sun Microsystems, Inc. Exporting 12C controller interfaces for 12C slave devices using IPMI micro-controller
US7093155B2 (en) 2003-11-18 2006-08-15 Hitachi, Ltd. Information processing system and method for path failover
US20050116546A1 (en) * 2003-12-02 2005-06-02 Zeighami Roy M. Power supply system
US20050146855A1 (en) 2004-01-07 2005-07-07 International Business Machines Corporation System and method for aligning and supporting interconnect systems
US7032052B2 (en) 2004-01-15 2006-04-18 Dell Products L.P. Information handling system capable of operating with multiple types of expansion cards in a common industry standard connector
US20050160214A1 (en) 2004-01-15 2005-07-21 Dell Products L.P. Information handling system capable of operating with multiple types of expansion cards in a common industry standard connector
US20050162830A1 (en) 2004-01-27 2005-07-28 Hewlett-Packard Development Company, L.P. Electronic system with a simplified enclosure
US20050182862A1 (en) 2004-02-12 2005-08-18 Ritz Andrew J. System and method for detecting DMA-generated memory corruption in a PCI express bus system
US7313643B2 (en) 2004-02-17 2007-12-25 Nec Electronics America, Inc. PCI-express to PCI/PCI X translator
US20050213513A1 (en) 2004-03-25 2005-09-29 Alcatel Full mesh LSP and full mesh T-LDP provisioning between provider edge routers in support of Layer-2 and Layer-3 Virtual Private Network services
US20050276017A1 (en) 2004-06-10 2005-12-15 Farid Aziz Common plenum and air intake airflow management for telecom equipment
US20050286187A1 (en) 2004-06-24 2005-12-29 Jeng-Shu Liu Esd preventing-able level shifters
US20050289278A1 (en) 2004-06-24 2005-12-29 Tan Thian A Apparatus and method for programmable completion tracking logic to support multiple virtual channels
US20050289271A1 (en) 2004-06-29 2005-12-29 Martinez Alberto J Circuitry to selectively produce MSI signals
US7062594B1 (en) 2004-06-30 2006-06-13 Emc Corporation Root complex connection system
US20080189577A1 (en) 2004-07-08 2008-08-07 International Business Machines Corporation Isolation of Input/Output Adapter Error Domains
US7152136B1 (en) 2004-08-03 2006-12-19 Altera Corporation Implementation of PCI express
US20060067069A1 (en) 2004-09-30 2006-03-30 Christopher Heard Electronic system with non-parallel arrays of circuit card assemblies
US20060085573A1 (en) 2004-10-15 2006-04-20 Dell Products L.P. Multi-context selection with PCI express to support hardware partitioning
US20060085150A1 (en) 2004-10-18 2006-04-20 Gorin Joseph M Phase noise compensation for phase noise measurements
US20060087813A1 (en) 2004-10-25 2006-04-27 International Business Machines Corporation System for airflow management in electronic enclosures
US20060087814A1 (en) 2004-10-25 2006-04-27 International Business Machines Corporation System for airflow management in electronic enclosures
US20060095607A1 (en) 2004-10-29 2006-05-04 Lim Su W PCI to PCI express protocol conversion
US20100005531A1 (en) 2004-12-23 2010-01-07 Kenneth Largman Isolated multiplexed multi-dimensional processing in a virtual processing space having virus, spyware, and hacker protection features
US20070186074A1 (en) 2005-01-14 2007-08-09 Bradford Jeffrey P Multiple page size address translation incorporating page size prediction
US7558348B1 (en) 2005-01-24 2009-07-07 Nvidia Corporation Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications
US7219181B2 (en) 2005-02-03 2007-05-15 Cisco Technology, Inc. Dual use modular PCI/PCI express interface
US7519647B2 (en) 2005-02-09 2009-04-14 International Business Machines Corporation System and method for providing a decimal multiply algorithm using a double adder
US7370224B1 (en) 2005-02-17 2008-05-06 Alcatel Usa Sourcing, Inc System and method for enabling redundancy in PCI-Express architecture
US20060195644A1 (en) 2005-02-25 2006-08-31 International Business Machines Corporation Interrupt mechanism on an IO adapter that supports virtualization
US7546386B2 (en) 2005-02-25 2009-06-09 International Business Machines Corporation Method for virtual resource initialization on a physical adapter that supports virtual resources
US20090144462A1 (en) 2005-02-28 2009-06-04 International Business Machines Corporation Method and System for Fully Trusted Adapter Validation of Addresses Referenced in a Virtual Host Transfer Request
US7464174B1 (en) 2005-03-07 2008-12-09 Pericom Semiconductor Corp. Shared network-interface controller (NIC) using advanced switching (AS) turn-pool routing field to select from among multiple contexts for multiple processors
US20060206639A1 (en) 2005-03-14 2006-09-14 Phison Electronics Corp. [virtual ide card reader with pci express]
US7535828B2 (en) 2005-03-18 2009-05-19 Cisco Technology, Inc. Algorithm for backup PE selection
US20060230208A1 (en) 2005-04-07 2006-10-12 Gregg Thomas A System and method for presenting interrupts
US20060236054A1 (en) 2005-04-19 2006-10-19 Manabu Kitamura Highly available external storage system
US7565463B2 (en) 2005-04-22 2009-07-21 Sun Microsystems, Inc. Scalable routing and addressing
US20060253619A1 (en) 2005-04-22 2006-11-09 Ola Torudbakken Virtualization for device sharing
US7480303B1 (en) 2005-05-16 2009-01-20 Pericom Semiconductor Corp. Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports
US20060288130A1 (en) 2005-06-21 2006-12-21 Rajesh Madukkarumukumana Address window support for direct memory access translation
US20070008663A1 (en) 2005-07-08 2007-01-11 Fujitsu Limited Electronic apparatus having DC voltage conversion function, and DC voltage converter
US7631097B2 (en) 2005-07-21 2009-12-08 National Instruments Corporation Method and apparatus for optimizing the responsiveness and throughput of a system performing packetized data transfers using a transfer count mark
US7525957B2 (en) 2005-09-01 2009-04-28 Emulex Design & Manufacturing Corporation Input/output router for storage networks
US20070262891A1 (en) 2005-09-09 2007-11-15 Woodral David E Method and system for synchronizing bit streams for pci express devices
US20070069585A1 (en) 2005-09-29 2007-03-29 International Business Machines Corporation Fail safe redundant power supply in a multi-node computer system
US20070073955A1 (en) 2005-09-29 2007-03-29 Joseph Murray Multi-function PCI device
US20070078996A1 (en) 2005-10-04 2007-04-05 Wei-Che Chen Method for managing a network appliance and transparent configurable network appliance
US20080270853A1 (en) 2005-10-27 2008-10-30 International Business Machines Corporation Method of Routing I/O Adapter Error Messages in a Multi-Host Environment
US20070136554A1 (en) 2005-12-12 2007-06-14 Giora Biran Memory operations in a virtualized system
US20080259555A1 (en) 2006-01-13 2008-10-23 Sun Microsystems, Inc. Modular blade server
US20070211430A1 (en) 2006-01-13 2007-09-13 Sun Microsystems, Inc. Compact rackmount server
US20080192431A1 (en) 2006-01-13 2008-08-14 Sun Microsystems, Inc. Compact rackmount server
US20070168636A1 (en) 2006-01-17 2007-07-19 Hummel Mark D Chained Hybrid IOMMU
US20070183393A1 (en) 2006-02-07 2007-08-09 Boyd William T Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system
US20070226386A1 (en) 2006-02-17 2007-09-27 Neteffect, Inc. Method and apparatus for using a single multi-function adapter with different operating systems
US8032684B2 (en) 2006-02-28 2011-10-04 Emulex Design And Manufacturing Corporation Programmable bridge header structures
US20110131359A1 (en) 2006-02-28 2011-06-02 Emulex Design And Manufacturing Corporation Programmable bridge header structures
US20070245041A1 (en) 2006-03-21 2007-10-18 Binh Hua Method to improve system DMA mapping while substantially reducing memory fragmentation
US20070226523A1 (en) * 2006-03-23 2007-09-27 Inventec Corporation System for controlling sequential startup of hard disks
US20070273018A1 (en) 2006-03-29 2007-11-29 Kabushiki Kaisha Toshiba Semiconductor apparatus and method for manufacturing the same
US20070239925A1 (en) 2006-04-11 2007-10-11 Nec Corporation PCI express link, multi host computer system, and method of reconfiguring PCI express link
US20070273401A1 (en) 2006-04-20 2007-11-29 Naoki Kiryu Systems and Methods for Improved Fault Coverage of LBIST Testing
US7613847B2 (en) 2006-05-16 2009-11-03 Hewlett-Packard Development Company, L.P. Partially virtualizing an I/O device for use by virtual machines
US20070271559A1 (en) 2006-05-17 2007-11-22 International Business Machines Corporation Virtualization of infiniband host channel adapter interruptions
US20090210527A1 (en) 2006-05-24 2009-08-20 Masahiro Kawato Virtual Machine Management Apparatus, and Virtual Machine Management Method and Program
US20070274039A1 (en) 2006-05-25 2007-11-29 Motorola, Inc. Embedded computer chassis with redundant fan trays
US7457900B2 (en) 2006-06-20 2008-11-25 Intel Corporation Method for discovering and partitioning PCI devices
US20090240849A1 (en) 2006-08-01 2009-09-24 International Business Machines Corporation System and Method for Distributing Virtual Input/Output Operations Across Multiple Logical Partitions
US7594144B2 (en) 2006-08-14 2009-09-22 International Business Machines Corporation Handling fatal computer hardware errors
US20080043405A1 (en) 2006-08-16 2008-02-21 Tyan Computer Corporation Chassis partition architecture for multi-processor system
US20090125666A1 (en) 2006-08-22 2009-05-14 International Business Machines Corporation Dynamically scalable queues for performance driven pci express memory traffic
US20080126648A1 (en) 2006-08-28 2008-05-29 Sean Thomas Brownlow Message Signaled Interrupt Management for a Computer Input/Output Fabric Incorporating Platform Independent Interrupt Manager
US20080069141A1 (en) 2006-09-20 2008-03-20 Reuters America Inc. Messaging model and architecture
US7627723B1 (en) 2006-09-21 2009-12-01 Nvidia Corporation Atomic memory operators in a parallel processor
US20080077817A1 (en) * 2006-09-26 2008-03-27 Dell Products L.P. Apparatus and Methods for Managing Power in an Information Handling System
US20080126652A1 (en) 2006-09-27 2008-05-29 Intel Corporation Managing Interrupts in a Partitioned Platform
US20080091851A1 (en) 2006-10-10 2008-04-17 Palm, Inc. System and method for dynamic audio buffer management
US20080091915A1 (en) 2006-10-17 2008-04-17 Moertl Daniel F Apparatus and Method for Communicating with a Memory Registration Enabled Adapter Using Cached Address Translations
US20080091868A1 (en) 2006-10-17 2008-04-17 Shay Mizrachi Method and System for Delayed Completion Coalescing
US7660912B2 (en) 2006-10-18 2010-02-09 International Business Machines Corporation I/O adapter LPAR isolation in a hypertransport environment
US20080114906A1 (en) 2006-11-13 2008-05-15 Hummel Mark D Efficiently Controlling Special Memory Mapped System Accesses
US7624235B2 (en) 2006-11-30 2009-11-24 Apple Inc. Cache used both as cache and staging buffer
US20080147943A1 (en) 2006-12-19 2008-06-19 Douglas M Freimuth System and method for migration of a virtual endpoint from one virtual plane to another
US20080148295A1 (en) 2006-12-19 2008-06-19 Freimuth Douglas M System and method for migration of single root stateless virtual functions
US20080162865A1 (en) 2006-12-29 2008-07-03 Koufaty David A Partitioning memory mapped device configuration space
US7617340B2 (en) 2007-01-09 2009-11-10 International Business Machines Corporation I/O adapter LPAR isolation with assigned memory space
US20080168208A1 (en) 2007-01-09 2008-07-10 International Business Machines Corporation I/O Adapter LPAR Isolation In A Hypertransport Environment With Assigned Memory Space Indexing a TVT Via Unit IDs
US20080222406A1 (en) 2007-03-06 2008-09-11 Nec Corporation Hot-pluggable information processing device and setting method
US20080239687A1 (en) 2007-03-29 2008-10-02 Leigh Kevin B Server infrastructure having independent backplanes to distribute power and to route signals
US20080239945A1 (en) 2007-03-30 2008-10-02 International Business Machines Corporation Peripheral component switch having automatic link failover
US20080263246A1 (en) 2007-04-17 2008-10-23 Larson Chad J System and Method for Balancing PCI-Express Bandwidth
US20080288661A1 (en) 2007-05-16 2008-11-20 Michael Galles Method and system to map virtual i/o devices and resources to a standard i/o bus
US7617345B2 (en) 2007-07-02 2009-11-10 International Business Machines Corporation Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
US20090037682A1 (en) 2007-08-02 2009-02-05 International Business Machines Corporation Hypervisor-enforced isolation of entities within a single logical partition's virtual address space
WO2009027189A1 (en) 2007-08-29 2009-03-05 International Business Machines Corporation Autonomic pci express hardware detection and failover mechanism
US20090070760A1 (en) 2007-09-06 2009-03-12 Mukund Khatri Virtual Machine (VM) Migration Between Processor Architectures
US7873851B1 (en) * 2007-09-28 2011-01-18 Emc Corporation Powering disk drive spinup
US20090144731A1 (en) 2007-12-03 2009-06-04 Brown Aaron C System and method for distribution of resources for an i/o virtualized (iov) adapter and management of the adapter through an iov management partition
US7836254B2 (en) 2007-12-18 2010-11-16 International Business Machines Corporation Cache injection using speculation
US20090182966A1 (en) 2008-01-11 2009-07-16 International Business Machines Corporation Dynamic address translation with frame management
US20090182969A1 (en) 2008-01-16 2009-07-16 Steven Paul Norgaard Dynamic allocation of dma buffers in input/output adaptors
US20100312894A1 (en) 2008-02-05 2010-12-09 Nec Corporation Resource allocation
US20090210646A1 (en) 2008-02-14 2009-08-20 Bauman Ellen M Cross Adapter Shared Address Translation Tables
US20090222814A1 (en) 2008-02-28 2009-09-03 Sony Ericsson Mobile Communications Ab Selective exposure to usb device functionality for a virtual machine
US20090234987A1 (en) 2008-03-12 2009-09-17 Mips Technologies, Inc. Efficient, Scalable and High Performance Mechanism for Handling IO Requests
US20110219161A1 (en) 2008-03-26 2011-09-08 Lsi Corporation System and method for providing address decode and virtual function (vf) migration support in a peripheral component interconnect express (pcie) multi-root input/output virtualization (iov) environment
US7676617B2 (en) 2008-03-31 2010-03-09 Lsi Corporation Posted memory write verification
US20090276774A1 (en) 2008-05-01 2009-11-05 Junji Kinoshita Access control for virtual machines in an information system
US20090276773A1 (en) 2008-05-05 2009-11-05 International Business Machines Corporation Multi-Root I/O Virtualization Using Separate Management Facilities of Multiple Logical Partitions
US20090276551A1 (en) 2008-05-05 2009-11-05 International Business Machines Corporation Native and Non-Native I/O Virtualization in a Single Adapter
US20090328035A1 (en) 2008-06-27 2009-12-31 Microsoft Corporation Lazy Handling of End of Interrupt Messages in a Virtualized Environment
US20100005234A1 (en) 2008-06-30 2010-01-07 Ganga Ilango S Enabling functional dependency in a multi-function device
US20100027559A1 (en) 2008-07-31 2010-02-04 Hung-Ming Lin Transmission device and data extended transmission method
US20100042999A1 (en) 2008-08-15 2010-02-18 International Business Machines Corporation Transactional quality of service in event stream processing middleware
US20100077117A1 (en) 2008-09-22 2010-03-25 Micron Technology, Inc. SATA MASS STORAGE DEVICE EMULATION ON A PCIe INTERFACE
US20100169674A1 (en) * 2008-09-26 2010-07-01 Fujitsu Limited Power-source control system and power-source control method
US8082466B2 (en) 2008-10-30 2011-12-20 Hitachi, Ltd. Storage device, and data path failover method of internal network of storage controller
US20100115329A1 (en) 2008-10-30 2010-05-06 Hitachi, Ltd. Storage Device, and Data path Failover Method of Internal Network of Storage Controller
US20100131359A1 (en) 2008-11-26 2010-05-27 Yahoo! Inc. System and method for securing invocations for serving advertisements and instrumentation in online advertising
US8046627B2 (en) 2008-12-05 2011-10-25 Hitachi, Ltd. Server failover control method and apparatus and computer system group
US20100146089A1 (en) 2008-12-09 2010-06-10 International Business Machines Corporation Use of Peripheral Component Interconnect Input/Output Virtualization Devices to Create High-Speed, Low-Latency Interconnect
US20100157463A1 (en) * 2008-12-18 2010-06-24 Arizono Yukiko Disk drive spin control
US20100211714A1 (en) 2009-02-13 2010-08-19 Unisys Corporation Method, system, and apparatus for transferring data between system memory and input/output busses
US8140917B2 (en) 2009-03-13 2012-03-20 Hitachi, Ltd. Stream recovery method, stream recovery program and failure recovery apparatus
US8041811B2 (en) 2009-04-21 2011-10-18 Alcatel Lucent Multi-chassis component corrector and associator engine
US20100287209A1 (en) 2009-05-05 2010-11-11 Paul A. Lipari System, method and computer readable medium for binding authored content to the events used to generate the content
US20110029696A1 (en) 2009-07-28 2011-02-03 Oki Semiconductor Co., Ltd. Information processing device
US20110029734A1 (en) 2009-07-29 2011-02-03 Solarflare Communications Inc Controller Integration
US20110265134A1 (en) 2009-11-04 2011-10-27 Pawan Jaggi Switchable multi-channel data transcoding and transrating system
US20110258352A1 (en) 2010-04-20 2011-10-20 Emulex Design & Manufacturing Corporation Inline PCI-IOV Adapter
US20110320861A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Switch failover control in a multiprocessor computer system
US20110320674A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Upbound input/output expansion request and response processing in a pcie architecture
US20110320602A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Discovery of logical images at storage area network endpoints
US20110317743A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Spread spectrum wireless communication code for data center environments
US20110317351A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Server drawer
US20110320892A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Memory error isolation and recovery in a multiprocessor computer system
US20110320703A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Associating input/output device requests with memory associated with a logical partition
US20110320670A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Connected input/output hub management
US20110320666A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Input/output (i/o) expansion response processing in a peripheral component interconnect express (pcie) environment
US20110320887A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Scalable i/o adapter function level error detection, isolation, and reporting
US20110320653A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation System and method for routing i/o expansion requests and responses in a pcie architecture
US20110320675A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation SYSTEM AND METHOD FOR DOWNBOUND I/O EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIe ARCHITECTURE

Non-Patent Citations (64)

* Cited by examiner, † Cited by third party
Title
"DMA Engines Bring Mulicast to PCI Express Systems," http://electronicdesign.com, Aug. 13, 2009, 3 pages.
"I/O Virtualization and AMD's IOMMU," AMD Developer Central, http://developer.amd.com/documentation/articles/pages.892006101.aspx, Aug. 9, 2006.
"IBM Enhances the IBM eServer zSeries 990 Family of Servers," Hardware Announcement, Oct. 7, 2003, pp. 1-11.
"Intel (registered trademark) Itanium (registered trademark) Architecture Software Developer's Manual," vol. 2, Rev. 2.2, Jan. 2006.
"z/VM: General Information Manual," IBM Publication No. GC24-5991-05, May 2003.
Baumann, Andrew, et al., "The Multikernel: A New OS Architecture for Scalable Multicore Systems," Oct. 2009, SOSP'09, Oct. 11-14, 2009, Big Sky, Montana, USA, pp. 29-43.
Crawford et al. "Accelerating Computing with the Cell Broadband Engine Processor"; CF'08, May 5-7, 2008; Ischia, Italy; Copyright 2008 ACM 978-1-60558-077.
Darren Abramson et al.; "Intel Virtualization Technology for Directed I/O"; Intel Technology Journal, vol. 10, Issue 3, Aug. 10, 2006; pp. 1-16.
Dolphin Interconnect Solutions; MySQL Acceleration Solutions; Solid State Storage; Embeded and HPC Solutions; "DXH510 PCI Express Host Adapter" ; ww.dolphinics.com/products/pent-dxseries-dsh510.html downloaded Jun. 10, 2010.
Final Office Action dated Aug. 30, 2012 for U.S. Appl. No. 12/821,245; pp. 1-28.
Final Office Action dated Jul. 19, 2012 for U.S. Appl. No. 12/821,250, pp. 1-23.
Final Office Action dated Sep. 13, 2012 for U.S. Appl. No. 12/821,256; pp. 1-23.
Final Office Action received Oct. 10, 2012 for U.S. Appl. No. 12/821,221; p. 1-15.
Huang, Wei et al., "A Case for High Performance Computing with Virtual Machines," ISC '06, Jun3 28 30, Carins, Queensland, Australia, pp. 125-134, Jun. 3, 2006.
International Search Report for PCT/EP2011/059810, Sep. 14, 2011.
Internet Article, "Large Page Support in the Lunux Kernel," http://Iwn.net./Articles/6969/.
Internet Article, "Large Page Support in the Lunux Kernel," http://Iwn.net./Articles/6969/<retrieved on Jan. 26, 2010>.
J. Regula, "Using Non-transparent Bridging in PCI Express Systems", PLX Technology, Inc., pp. 1-31; Published: Jun. 1, 2004.
Jack Regula; "Ethernet Tunneling through PCI Express Inter-Processor Communication, Low Latency Storage IO Source"; www.wwpi.com; publisher: Computer Technology Review; Jan. 19, 2009.
K. Vaidyanathan et al.; "Exploiting RDMA Operations for Providing Efficient Fine-Grained Resource Monitoring in Cluster-Based Servers"; Jun. 2006; pp. 10; Downloaded: Apr. 13, 2010 at 18:53:46 UTC from IEEE Xplore. 1-4244-0328-6/06.
Mysore Shashidhar et al., "Understanding and Visualizing Full Systems with Data Flow Tomography" SPOLOS '08, Mar. 1-5, 2008, Seattle, Washington, USA, pp. 211-221.
Narayanan Ganapathy et al.; Papers-USENIX Annual Teleconference (No. 98); Entitled: "General Purpose Operating System Support for Multiple Page Sizes" 1998; pp. 1-9.
Narayanan Ganapathy et al.; Papers—USENIX Annual Teleconference (No. 98); Entitled: "General Purpose Operating System Support for Multiple Page Sizes" 1998; pp. 1-9.
Non Final Office Action received Mar. 15, 2012 for U.S. Appl. No. 12/821,242; pp. 1-28.
Non Final Office Action received May 4, 2012 for U.S. Appl. No. 12/821,256; pp. 1-36.
Non Final Office Action recieved May 8, 2012 for U.S. Appl. No. 12/821,243; pp. 1-28.
Non-final Office Action dated Jun. 5, 2012 for U.S. Appl. No. 12/821,221; pp. 1-14.
Non-final Office Action dated Sep. 26, 2012 for U.S. Appl. No. 12/821,243; pp. 1-25.
Non-Final Office Action mail date Jan. 10, 2011.
Non-final office Action received for U.S. Appl. No. 12/821,239 dated Nov. 8, 2012; pp. 1-44.
Non-final Office Action received Oct. 11, 2012 for U.S. Appl. No. 12/821,247; pp. 1-46.
Notice of Allowance dated Sep. 19, 2012 for U.S. Appl. No. 12/821,224; pp. 1-8.
Paulsen, Erik; "Local Memory Coaxes Top Speed from SCSI Masters"; Electronic Design, v. 41, (Apr. 15, 1993) p. 75-6+.
PCI Express Base Specification Rev 1.0a, Apr. 15, 2003 p. 1-2, 31, 35-36, 43-44, 49-51, 55, 59-62, 74, 101.
Robert F. Kern, "IBM System z & DS8000 Technology Synergy", IBM ATS Americas Disk Storage; Jul. 21, 2009, pp. 1-25.
Swift, Micael M. et al., "Improving the Reliability of Commodity Operating Systems," ACM Transactions on Computer Systems, vol. 23, No. 1, Feb. 2005, pp. 77-110.
Szwed et al.; "Managing Connected PCI Express Root Complexes"; Dated: Dec. 23, 2009-6 pages.
Szwed et al.; "Managing Connected PCI Express Root Complexes"; Dated: Dec. 23, 2009—6 pages.
Talluri et al., "A New Page Table for 64-bit Address Spaces," ACM SIGOPS Operating Systems Review, vol. 29, Issue 5 (Dec. 1995), pp. 194-200.
U.S. Appl. No. 12/821,124, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,181, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,182, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,185, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,191, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,221, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,221, Final Office Action mail date Jun. 15, 2011.
U.S. Appl. No. 12/821,222, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,224, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,239, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,242, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,243, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,245, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,247, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,248, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,250, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,256, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,271, filed Jun. 23, 2010.
U.S. Appl. No. 12/821,648, filed Jun. 23, 2010.
VTdHowTo-Xen Wiki; Downloaded-Apr. 16, 2010; pp. 1-5; http://wiki.xensource.com/xenwiki/VTdHowTo.
VTdHowTo—Xen Wiki; Downloaded—Apr. 16, 2010; pp. 1-5; http://wiki.xensource.com/xenwiki/VTdHowTo.
Winwood, Simon, et al., "Multiple Page Size Support in the Linux Kernel", Proceedings of Ottawa Linux Symposium, 2002.
Xu, Min et al., "Towards a VMM-based Usage Control Framework for OS Kernel Integrity Protection," SACMAT '07, Jun. 20-22, 2007, Sophia Antipolis, France, pp. 71-80.
z/Architecture Principles of Operation, Feb. 2009; pp. 1-1344.
z/VM: Running Guest Operating Systems, IBM Publication No. SC24-5997-02, Oct. 2001.

Also Published As

Publication number Publication date
US20110320796A1 (en) 2011-12-29

Similar Documents

Publication Publication Date Title
Brown et al. Toward energy-efficient computing.
US8874950B2 (en) Power management for input/output devices
CN1947096B (en) Dynamic migration of virtual machine computer programs
US7900069B2 (en) Dynamic power reduction
AU2013274662B2 (en) Unified storage/VDI provisioning methodology
US8756369B2 (en) Priority command queues for low latency solid state drives
US8762752B2 (en) System and method for remotely managing electric power usage of target computers
CN100381978C (en) System and method for power management of plural information handling systems
US8051316B2 (en) System and method for managing power supply units
US20120198261A1 (en) Controlling power sequence in a blade center environment
CN101216750B (en) System, method, and module for reducing power states for storage devices and associated logical volumes
US20080313492A1 (en) Adjusting a Cooling Device and a Server in Response to a Thermal Event
CN101276301B (en) Method and apparatus for allocating resources between the data backup system in the backup task
US20120179937A1 (en) Storage system and control method thereof
JP5324666B2 (en) Storage system
US9904346B2 (en) Methods and apparatus to improve turbo performance for events handling
CN101350737B (en) Ipmi systems and electronic apparatus and memory sharing method
US8909957B2 (en) Dynamic voltage adjustment to computer system memory
US8751836B1 (en) Data storage system and method for monitoring and controlling the power budget in a drive enclosure housing data storage devices
CN1694086A (en) Task-oriented processing as an auxiliary to primary computing environments
EP2780799B1 (en) Throttle disk i/o using disk drive simulation model
JP2010146630A (en) Disk drive and disk array system
KR20090107490A (en) Maximum power usage setting for computing device
JP2004078935A (en) Method for managing operation voltage of blade in bladed architecture system
US7921203B2 (en) Specifying associations among attributes of entities in

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DECUSATIS, CASIMER M.;KRISHNAMURTHY, RAJARAM B.;ONGHENA, MICHAEL;AND OTHERS;SIGNING DATES FROM 20100525 TO 20100602;REEL/FRAME:024579/0612

FEPP

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)

FP Expired due to failure to pay maintenance fee

Effective date: 20180311