DE60012735D1 - Verfahren zur unterscheidung von verschiedenen typen von abtastfehlern, rechnerbasierte schaltungsemulation und fehlerdetektionssystem - Google Patents

Verfahren zur unterscheidung von verschiedenen typen von abtastfehlern, rechnerbasierte schaltungsemulation und fehlerdetektionssystem

Info

Publication number
DE60012735D1
DE60012735D1 DE60012735T DE60012735T DE60012735D1 DE 60012735 D1 DE60012735 D1 DE 60012735D1 DE 60012735 T DE60012735 T DE 60012735T DE 60012735 T DE60012735 T DE 60012735T DE 60012735 D1 DE60012735 D1 DE 60012735D1
Authority
DE
Germany
Prior art keywords
computer
different types
detection system
error detection
based circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60012735T
Other languages
English (en)
Other versions
DE60012735T2 (de
Inventor
Laurent Souef
Jerome Bombal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE60012735D1 publication Critical patent/DE60012735D1/de
Publication of DE60012735T2 publication Critical patent/DE60012735T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318591—Tools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE60012735T 1999-11-18 2000-11-13 Verfahren zur unterscheidung von verschiedenen typen von abtastfehlern, rechnerbasierte schaltungsemulation und fehlerdetektionssystem Expired - Lifetime DE60012735T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US443883 1999-11-18
US09/443,883 US6970815B1 (en) 1999-11-18 1999-11-18 Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system
PCT/US2000/042148 WO2001037091A2 (en) 1999-11-18 2000-11-13 Method of discriminating between different types of scan failures, a computer implemented circuit simulation and fault detection system

Publications (2)

Publication Number Publication Date
DE60012735D1 true DE60012735D1 (de) 2004-09-09
DE60012735T2 DE60012735T2 (de) 2005-08-04

Family

ID=23762554

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60012735T Expired - Lifetime DE60012735T2 (de) 1999-11-18 2000-11-13 Verfahren zur unterscheidung von verschiedenen typen von abtastfehlern, rechnerbasierte schaltungsemulation und fehlerdetektionssystem

Country Status (5)

Country Link
US (1) US6970815B1 (de)
EP (1) EP1188117B1 (de)
JP (1) JP2003515217A (de)
DE (1) DE60012735T2 (de)
WO (1) WO2001037091A2 (de)

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US6697982B2 (en) * 2001-05-04 2004-02-24 Texas Instruments Incorporated Generating netlist test vectors by stripping references to a pseudo input
US20060136795A1 (en) * 2004-12-17 2006-06-22 Lsi Logic Corporation Method of testing scan chain integrity and tester setup for scan block testing
US7607057B2 (en) * 2004-12-28 2009-10-20 Lsi Corporation Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
US7543204B2 (en) * 2005-07-28 2009-06-02 International Business Machines Corporation Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
JP4839856B2 (ja) * 2006-01-23 2011-12-21 富士通株式会社 スキャンチェーン抽出プログラム、スキャンチェーン抽出方法及び試験装置
US8060851B2 (en) * 2006-10-13 2011-11-15 Verigy (Singapore) Pte. Ltd. Method for operating a secure semiconductor IP server to support failure analysis
US7945417B2 (en) * 2007-07-30 2011-05-17 Carl Z. Zhou Method of digital extraction for accurate failure diagnosis
US8164345B2 (en) * 2008-05-16 2012-04-24 Rutgers, The State University Of New Jersey Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability
GB2462897A (en) * 2008-09-02 2010-03-03 Ibm Debugging a hardware device comprising combinatorial logic
US8990648B2 (en) * 2012-03-28 2015-03-24 International Business Machines Corporation Optimized synchronous scan flip flop circuit
US9099173B2 (en) * 2012-12-14 2015-08-04 Virtium Technology, Inc. Classifying flash devices using ECC
US9081932B2 (en) * 2013-02-01 2015-07-14 Qualcomm Incorporated System and method to design and test a yield sensitive circuit
US10838449B2 (en) * 2018-07-05 2020-11-17 International Business Machines Corporation Automatic detection of clock grid misalignments and automatic realignment
US10914785B2 (en) 2018-11-13 2021-02-09 Realtek Semiconductor Corporation Testing method and testing system
US10598730B1 (en) 2018-11-13 2020-03-24 Realtek Semiconductor Corporation Testing method and testing system
US11879942B1 (en) * 2022-08-31 2024-01-23 Micron Technology, Inc. Core and interface scan testing architecture and methodology

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US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
US5406497A (en) 1990-09-05 1995-04-11 Vlsi Technology, Inc. Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler including a cell library
US5253255A (en) 1990-11-02 1993-10-12 Intel Corporation Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip
US5910958A (en) * 1991-08-14 1999-06-08 Vlsi Technology, Inc. Automatic generation of test vectors for sequential circuits
US5331570A (en) * 1992-03-27 1994-07-19 Mitsubishi Electric Research Laboratories, Inc. Method for generating test access procedures
US5404526A (en) 1992-10-20 1995-04-04 Dosch; Daniel G. Improved method for accessing machine state information
US5550839A (en) 1993-03-12 1996-08-27 Xilinx, Inc. Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays
US5574853A (en) * 1994-01-03 1996-11-12 Texas Instruments Incorporated Testing integrated circuit designs on a computer simulation using modified serialized scan patterns
WO1995030230A2 (en) 1994-04-28 1995-11-09 Apple Computer, Inc. Scannable d-flip-flop with system independent clocking
US5633813A (en) * 1994-05-04 1997-05-27 Srinivasan; Seshan R. Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits
US5572712A (en) * 1994-09-30 1996-11-05 Vlsi Technology, Inc. Method and apparatus for making integrated circuits with built-in self-test
US5748497A (en) * 1994-10-31 1998-05-05 Texas Instruments Incorporated System and method for improving fault coverage of an electric circuit
US5517637A (en) * 1994-12-09 1996-05-14 Motorola, Inc. Method for testing a test architecture within a circuit
US5596585A (en) * 1995-06-07 1997-01-21 Advanced Micro Devices, Inc. Performance driven BIST technique
US5862149A (en) 1995-08-29 1999-01-19 Unisys Corporation Method of partitioning logic designs for automatic test pattern generation based on logical registers
US5684808A (en) 1995-09-19 1997-11-04 Unisys Corporation System and method for satisfying mutually exclusive gating requirements in automatic test pattern generation systems
US5703789A (en) 1995-12-29 1997-12-30 Synopsys, Inc. Test ready compiler for design for test synthesis
US5903578A (en) * 1996-03-08 1999-05-11 Lsi Logic Corporation Test shells for protecting proprietary information in asic cores
US5696771A (en) 1996-05-17 1997-12-09 Synopsys, Inc. Method and apparatus for performing partial unscan and near full scan within design for test applications
US5812561A (en) 1996-09-03 1998-09-22 Motorola, Inc. Scan based testing of an integrated circuit for compliance with timing specifications
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
US5831993A (en) 1997-03-17 1998-11-03 Lsi Logic Corporation Method and apparatus for scan chain with reduced delay penalty
US5909453A (en) 1997-07-02 1999-06-01 Xilinx, Inc. Lookahead structure for fast scan testing
US5920575A (en) 1997-09-19 1999-07-06 International Business Machines Corporation VLSI test circuit apparatus and method
US5983376A (en) * 1997-09-24 1999-11-09 Sun Microsystems, Inc. Automated scan insertion flow for control block design
US6256770B1 (en) * 1997-10-17 2001-07-03 Lucent Technologies Inc. Register transfer level (RTL) based scan insertion for integrated circuit design processes
US6175946B1 (en) * 1997-10-20 2001-01-16 O-In Design Automation Method for automatically generating checkers for finding functional defects in a description of a circuit
US6463560B1 (en) * 1999-06-23 2002-10-08 Agere Systems Guardian Corp. Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits

Also Published As

Publication number Publication date
DE60012735T2 (de) 2005-08-04
WO2001037091A3 (en) 2002-01-03
JP2003515217A (ja) 2003-04-22
EP1188117B1 (de) 2004-08-04
US6970815B1 (en) 2005-11-29
EP1188117A2 (de) 2002-03-20
WO2001037091A2 (en) 2001-05-25

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL