DE60010412D1 - Integrierte Schaltung mit Überwachungsmittel von internen Bussen - Google Patents

Integrierte Schaltung mit Überwachungsmittel von internen Bussen

Info

Publication number
DE60010412D1
DE60010412D1 DE60010412T DE60010412T DE60010412D1 DE 60010412 D1 DE60010412 D1 DE 60010412D1 DE 60010412 T DE60010412 T DE 60010412T DE 60010412 T DE60010412 T DE 60010412T DE 60010412 D1 DE60010412 D1 DE 60010412D1
Authority
DE
Germany
Prior art keywords
integrated circuit
monitoring means
internal buses
buses
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60010412T
Other languages
English (en)
Other versions
DE60010412T2 (de
Inventor
Tomohiko Kitamura
Masataka Osaka
Tsutomu Sekibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE60010412D1 publication Critical patent/DE60010412D1/de
Publication of DE60010412T2 publication Critical patent/DE60010412T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/366—Software debugging using diagnostics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G06F11/364—Software debugging by tracing the execution of the program tracing values on a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)
DE60010412T 1999-11-17 2000-11-15 Integrierte Schaltung mit Überwachungsmittel von internen Bussen Expired - Fee Related DE60010412T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32677699 1999-11-17
JP32677699A JP2001142869A (ja) 1999-11-17 1999-11-17 システム集積回路

Publications (2)

Publication Number Publication Date
DE60010412D1 true DE60010412D1 (de) 2004-06-09
DE60010412T2 DE60010412T2 (de) 2004-09-16

Family

ID=18191583

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60010412T Expired - Fee Related DE60010412T2 (de) 1999-11-17 2000-11-15 Integrierte Schaltung mit Überwachungsmittel von internen Bussen

Country Status (5)

Country Link
US (1) US6804742B1 (de)
EP (1) EP1102169B1 (de)
JP (1) JP2001142869A (de)
KR (1) KR100732286B1 (de)
DE (1) DE60010412T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3900470B2 (ja) * 2002-01-08 2007-04-04 インターナショナル・ビジネス・マシーンズ・コーポレーション ディジタル信号測定装置及びトラフィック観測方法
WO2005096168A1 (ja) * 2004-04-01 2005-10-13 Matsushita Electric Industrial Co., Ltd. 映像音声処理用集積回路
US7353317B2 (en) * 2004-12-28 2008-04-01 Intel Corporation Method and apparatus for implementing heterogeneous interconnects
US7613876B2 (en) * 2006-06-08 2009-11-03 Bitmicro Networks, Inc. Hybrid multi-tiered caching storage system
US7613049B2 (en) * 2007-01-08 2009-11-03 Macronix International Co., Ltd Method and system for a serial peripheral interface
JPWO2009096161A1 (ja) * 2008-01-29 2011-05-26 パナソニック株式会社 プロセッサ性能解析装置、方法及びシミュレータ
US9342445B2 (en) 2009-07-23 2016-05-17 Hgst Technologies Santa Ana, Inc. System and method for performing a direct memory access at a predetermined address in a flash storage
CN102137257B (zh) * 2011-03-01 2013-05-08 北京声迅电子有限公司 基于tms320dm642芯片的嵌入式h.264编码方法
US10558598B2 (en) * 2018-03-20 2020-02-11 Seagate Technology Llc Logic circuit that provides verification of signals used to interrupt server operation

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345580A (en) 1990-11-29 1994-09-06 Kabushiki Kaisha Toshiba Microprocessor device and emulator device thereof
JP2563708B2 (ja) 1990-11-29 1996-12-18 株式会社東芝 マイクロプロセッサ装置およびそれを用いたエミュレータ装置
JP2719052B2 (ja) * 1991-02-21 1998-02-25 三菱電機株式会社 マイクロコンピュータ
GB9116493D0 (en) * 1991-07-30 1991-09-11 Inmos Ltd Read and write circuitry for a memory
US5444722A (en) * 1993-02-17 1995-08-22 Unisys Corporation Memory module with address error detection
US5903911A (en) * 1993-06-22 1999-05-11 Dell Usa, L.P. Cache-based computer system employing memory control circuit and method for write allocation and data prefetch
US5857084A (en) * 1993-11-02 1999-01-05 Klein; Dean A. Hierarchical bus structure access system
US5568621A (en) * 1993-11-10 1996-10-22 Compaq Computer Corporation Cached subtractive decode addressing on a computer bus
JPH07253915A (ja) 1994-03-15 1995-10-03 Hitachi Ltd 性能測定機能を有するアクセス制御装置
FR2720173B1 (fr) 1994-05-20 1996-08-14 Sgs Thomson Microelectronics Circuit intégré comprenant des moyens pour arrêter l'exécution d'un programme d'instructions quand une combinaison de points d'arrêt est vérifiée.
US5918247A (en) * 1995-10-27 1999-06-29 Motorola, Inc. Method for canceling partial line fetch for cache when new data is requested during current fetch and invalidating portion of previously fetched data
US5867644A (en) 1996-09-10 1999-02-02 Hewlett Packard Company System and method for on-chip debug support and performance monitoring in a microprocessor
US5953263A (en) 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6026503A (en) 1997-08-12 2000-02-15 Telrad Communication And Electronic Industries Ltd. Device and method for debugging systems controlled by microprocessors

Also Published As

Publication number Publication date
EP1102169A1 (de) 2001-05-23
DE60010412T2 (de) 2004-09-16
EP1102169B1 (de) 2004-05-06
KR100732286B1 (ko) 2007-06-25
US6804742B1 (en) 2004-10-12
KR20010051746A (ko) 2001-06-25
JP2001142869A (ja) 2001-05-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee