DE60008789D1 - Bitfehlerkarten-kompression mit signaturanalyse - Google Patents

Bitfehlerkarten-kompression mit signaturanalyse

Info

Publication number
DE60008789D1
DE60008789D1 DE60008789T DE60008789T DE60008789D1 DE 60008789 D1 DE60008789 D1 DE 60008789D1 DE 60008789 T DE60008789 T DE 60008789T DE 60008789 T DE60008789 T DE 60008789T DE 60008789 D1 DE60008789 D1 DE 60008789D1
Authority
DE
Germany
Prior art keywords
fail
bit error
signature analysis
areas
bit map
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60008789T
Other languages
English (en)
Other versions
DE60008789T2 (de
Inventor
Joerg Vollrath
Thomas Hladschik
Zschunke Andreas
Peter Oswald
Ulf Lederer
Rausch Harold
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE60008789D1 publication Critical patent/DE60008789D1/de
Application granted granted Critical
Publication of DE60008789T2 publication Critical patent/DE60008789T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31935—Storing data, e.g. failure memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60008789T 1999-12-07 2000-12-05 Bitfehlerkarten-kompression mit signaturanalyse Expired - Fee Related DE60008789T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/455,855 US6564346B1 (en) 1999-12-07 1999-12-07 Advanced bit fail map compression with fail signature analysis
US455855 1999-12-07
PCT/US2000/032847 WO2001042803A2 (en) 1999-12-07 2000-12-05 Bit fail map compression with fail signature analysis

Publications (2)

Publication Number Publication Date
DE60008789D1 true DE60008789D1 (de) 2004-04-08
DE60008789T2 DE60008789T2 (de) 2005-02-10

Family

ID=23810528

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60008789T Expired - Fee Related DE60008789T2 (de) 1999-12-07 2000-12-05 Bitfehlerkarten-kompression mit signaturanalyse

Country Status (6)

Country Link
US (1) US6564346B1 (de)
EP (1) EP1236051B1 (de)
KR (1) KR100483778B1 (de)
DE (1) DE60008789T2 (de)
TW (1) TW527490B (de)
WO (1) WO2001042803A2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10064329A1 (de) * 1999-12-27 2001-07-19 Mitsubishi Electric Corp Fehleranalyseverfahren, Kompressionsschwellenwertableitungsverfahren und Aufzeichnungsmedium
JP2001202795A (ja) * 2000-01-21 2001-07-27 Nec Corp メモリｌｓｉ不良解析装置および解析方法
JP3530457B2 (ja) * 2000-04-07 2004-05-24 Ｎｅｃエレクトロニクス株式会社 メモリｌｓｉ不良解析装置および解析方法
JP2001357697A (ja) * 2000-06-13 2001-12-26 Advantest Corp フェイル解析装置
KR20030048483A (ko) * 2000-11-28 2003-06-19 가부시키가이샤 아드반테스트 오류 분석장치
US6754858B2 (en) * 2001-03-29 2004-06-22 International Business Machines Corporation SDRAM address error detection method and apparatus
US6950971B2 (en) * 2001-11-05 2005-09-27 Infineon Technologies Ag Using data compression for faster testing of embedded memory
JP2003338196A (ja) * 2002-05-22 2003-11-28 Mitsubishi Electric Corp 不良解析方法
US20040083410A1 (en) * 2002-10-29 2004-04-29 Cutter Douglas J. Systems and methods to improve silicon debug of speed failures in memory arrays
DE10337284B4 (de) * 2003-08-13 2014-03-20 Qimonda Ag Integrierter Speicher mit einer Schaltung zum Funktionstest des integrierten Speichers sowie Verfahren zum Betrieb des integrierten Speichers
US7529988B1 (en) * 2003-09-02 2009-05-05 Advanced Micro Devices, Inc. Storage of descriptive information in user defined fields of failure bitmaps in integrated circuit technology development
US7698607B2 (en) * 2004-06-15 2010-04-13 Intel Corporation Repairing microdisplay frame buffers
DE102004036545B3 (de) * 2004-07-28 2006-03-16 Infineon Technologies Ag Integrierter Halbleiterspeicher mit redundanten Speicherzellen
US7836364B1 (en) 2006-05-30 2010-11-16 Marvell International Ltd. Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions
US8316206B2 (en) * 2007-02-12 2012-11-20 Marvell World Trade Ltd. Pilot placement for non-volatile memory
US7676775B2 (en) 2007-05-29 2010-03-09 International Business Machines Corporation Method to determine the root causes of failure patterns by using spatial correlation of tester data
JP2008299953A (ja) * 2007-05-31 2008-12-11 Toshiba Corp 半導体メモリの不良解析方法および不良解析システム
US20080319568A1 (en) * 2007-06-22 2008-12-25 International Business Machines Corporation Method and system for creating array defect paretos using electrical overlay of bitfail maps, photo limited yield, yield, and auto pattern recognition code data
US7694196B2 (en) * 2007-11-20 2010-04-06 Qimonda North America Corp. Self-diagnostic scheme for detecting errors
JP2011165249A (ja) * 2010-02-08 2011-08-25 Elpida Memory Inc 半導体装置
JP2012018052A (ja) * 2010-07-07 2012-01-26 Toshiba Corp 半導体装置の不良解析システム及び方法
KR101730497B1 (ko) * 2011-11-04 2017-04-27 삼성전자 주식회사 에러 정정 성능 신장 방법 및 이를 이용한 저장 장치
US9043638B1 (en) 2014-11-14 2015-05-26 Quanta Computer Inc. Method for enhancing memory fault tolerance
US9401222B1 (en) 2015-11-23 2016-07-26 International Business Machines Corporation Determining categories for memory fail conditions
US10101388B2 (en) 2015-12-15 2018-10-16 International Business Machines Corporation Method for enhanced semiconductor product diagnostic fail signature detection
US9946462B1 (en) 2016-02-15 2018-04-17 Seagate Technology Llc Address mapping table compression
KR20210141156A (ko) * 2020-05-15 2021-11-23 삼성전자주식회사 페이지 장애에 기초하여 메모리 고장을 예견하고, 예견되는 메모리 고장을 관리하는 시스템의 운영 체계 핸들링

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69121345T2 (de) * 1990-09-25 1997-01-23 Brother Ind Ltd Zeichenausgabegerät
JP3639636B2 (ja) * 1995-04-25 2005-04-20 株式会社ルネサステクノロジ 半導体ウェハの不良解析装置及び不良解析方法
JP3552175B2 (ja) * 1995-05-17 2004-08-11 株式会社アドバンテスト フェイルメモリ装置
US5720031A (en) * 1995-12-04 1998-02-17 Micron Technology, Inc. Method and apparatus for testing memory devices and displaying results of such tests
GB9623215D0 (en) * 1996-11-07 1997-01-08 Process Insight Limited Solid state memory test system with defect compression
US6035432A (en) * 1997-07-31 2000-03-07 Micron Electronics, Inc. System for remapping defective memory bit sets

Also Published As

Publication number Publication date
KR100483778B1 (ko) 2005-04-19
WO2001042803A2 (en) 2001-06-14
EP1236051A2 (de) 2002-09-04
DE60008789T2 (de) 2005-02-10
WO2001042803A3 (en) 2001-11-08
EP1236051B1 (de) 2004-03-03
KR20020060986A (ko) 2002-07-19
US6564346B1 (en) 2003-05-13
TW527490B (en) 2003-04-11

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee