DE60006992D1 - Mehrstufiger algorithmischer mustergenerator zur prüfung von ic-bausteinen - Google Patents

Mehrstufiger algorithmischer mustergenerator zur prüfung von ic-bausteinen

Info

Publication number
DE60006992D1
DE60006992D1 DE60006992T DE60006992T DE60006992D1 DE 60006992 D1 DE60006992 D1 DE 60006992D1 DE 60006992 T DE60006992 T DE 60006992T DE 60006992 T DE60006992 T DE 60006992T DE 60006992 D1 DE60006992 D1 DE 60006992D1
Authority
DE
Germany
Prior art keywords
testing
components
pattern generator
algorithmic pattern
stage algorithmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60006992T
Other languages
English (en)
Inventor
Vernon Rhodes
Davis Conklin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of DE60006992D1 publication Critical patent/DE60006992D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/31813Test pattern generators

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60006992T 1999-11-03 2000-10-24 Mehrstufiger algorithmischer mustergenerator zur prüfung von ic-bausteinen Expired - Lifetime DE60006992D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/432,965 US6415408B1 (en) 1999-11-03 1999-11-03 Multi-stage algorithmic pattern generator for testing IC chips
PCT/US2000/029301 WO2001033236A1 (en) 1999-11-03 2000-10-24 Multi-stage algorithmic pattern generator for testing ic chips

Publications (1)

Publication Number Publication Date
DE60006992D1 true DE60006992D1 (de) 2004-01-15

Family

ID=23718291

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60006992T Expired - Lifetime DE60006992D1 (de) 1999-11-03 2000-10-24 Mehrstufiger algorithmischer mustergenerator zur prüfung von ic-bausteinen

Country Status (5)

Country Link
US (1) US6415408B1 (de)
EP (1) EP1226444B1 (de)
JP (1) JP3591646B2 (de)
DE (1) DE60006992D1 (de)
WO (1) WO2001033236A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934900B1 (en) * 2001-06-25 2005-08-23 Global Unichip Corporation Test pattern generator for SRAM and DRAM
KR100487535B1 (ko) * 2002-08-14 2005-05-03 삼성전자주식회사 다른 종류의 반도체 장치들을 동시에 테스트하는 시스템
DE10322541A1 (de) * 2003-05-19 2004-12-16 Infineon Technologies Ag Speicherbaustein mit integrierter Adressscramblereinheit und Verfahren zum Verscrambeln einer Adresse in einem integrierten Speicher
US7228478B2 (en) * 2004-08-11 2007-06-05 International Business Machines Corporation Built-in self-test (BIST) for high performance circuits
WO2011086884A1 (ja) * 2010-01-15 2011-07-21 国立大学法人 奈良先端科学技術大学院大学 半導体集積回路のテストパターン生成方法、プログラム、およびコンピュータ読み取り可能な記録媒体
US9202592B2 (en) * 2013-12-30 2015-12-01 Unisys Corporation Systems and methods for memory management in a dynamic translation computer system
US9316689B2 (en) 2014-04-18 2016-04-19 Breker Verification Systems Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359569A (en) * 1991-10-29 1994-10-25 Hitachi Ltd. Semiconductor memory
US5390129A (en) * 1992-07-06 1995-02-14 Motay Electronics, Inc. Universal burn-in driver system and method therefor
US5696929A (en) * 1995-10-03 1997-12-09 Intel Corporation Flash EEPROM main memory in a computer system
JPH09244961A (ja) * 1996-03-08 1997-09-19 Mitsubishi Electric Corp フラッシュata−pcカード
US5883905A (en) * 1997-02-18 1999-03-16 Schlumberger Technologies, Inc. Pattern generator with extended register programming
US5923675A (en) * 1997-02-20 1999-07-13 Teradyne, Inc. Semiconductor tester for testing devices with embedded memory

Also Published As

Publication number Publication date
EP1226444B1 (de) 2003-12-03
WO2001033236A1 (en) 2001-05-10
JP3591646B2 (ja) 2004-11-24
US6415408B1 (en) 2002-07-02
JP2003513285A (ja) 2003-04-08
EP1226444A1 (de) 2002-07-31

Similar Documents

Publication Publication Date Title
DE60042825D1 (de) Vorrichtung zur überprüfung von spielkarten
DE69734379D1 (de) Vorrichtung zur Prüfung von integrierten Schaltungen
DE60029368D1 (de) Tintenstrahl-Prüfmuster
DE69936470D1 (de) Testkarte
DE69400884T2 (de) Fassung zum Testen von integrierten Schaltkreisen
DE50105056D1 (de) Vorrichtung zum Verbinden von Bauteilen
DE60001913D1 (de) Mustergenerator für eine testvorrichtung von paketbasierten speichern
DE50015692D1 (de) Vorrichtung zur fixierung von chirurgischen implantaten
DE60039668D1 (de) Gerät zur Fixmusterdetektion
DE69926215D1 (de) Verfahren und Schaltung zur Minimierung von Störsignalen in Phasenregelkreisen
DE19782246T1 (de) IC-Testgerät
DE50010729D1 (de) Gasgenerator
DE69806625D1 (de) Vorrichtung zum beleuchten von mustern
DE60013879D1 (de) Anfangsstufe eines mehrstufigen algorithmischen mustergenerator zur prüfung von ic-bausteinen
DE60006992D1 (de) Mehrstufiger algorithmischer mustergenerator zur prüfung von ic-bausteinen
DE60106395D1 (de) Verfahren zum lesen von elektronischen etiketten mittels gleichzeitiger identifizierung ihres kodes
DE60042518D1 (de) Verfahren zur speicherprüfung
DE60002775D1 (de) Vorrichtung zur Herstellung von elektronischen Schaltungen
DE69922775D1 (de) Elektronisches System zum Vorlegen von Angeboten
DE69827401D1 (de) Belastungsschaltung für ic-tester
DE60030603D1 (de) Vorrichtung zur Bilderkennung mit Verwendung von Teilmustern
DE69934604D1 (de) Vorrichtung zur prüfung von kondomen
DE50015432D1 (de) Prüfeinrichtung zum prüfen von langgestreckten gegenständen
FR2780792B1 (fr) Appareillage de test de puces electroniques
DE69822694D1 (de) Verfahren zum prüfgerechten Entwurf, Verfahren zur Prüfsequenzerzeugung und integrierte Halbleiterschaltung

Legal Events

Date Code Title Description
8332 No legal effect for de