DE60003273T2 - Verfahren und Vorrichtung zur Erzeugung einer Eingabeadresse - Google Patents

Verfahren und Vorrichtung zur Erzeugung einer Eingabeadresse Download PDF

Info

Publication number
DE60003273T2
DE60003273T2 DE60003273T DE60003273T DE60003273T2 DE 60003273 T2 DE60003273 T2 DE 60003273T2 DE 60003273 T DE60003273 T DE 60003273T DE 60003273 T DE60003273 T DE 60003273T DE 60003273 T2 DE60003273 T2 DE 60003273T2
Authority
DE
Germany
Prior art keywords
address
page
page table
region
hash
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60003273T
Other languages
German (de)
English (en)
Other versions
DE60003273D1 (de
Inventor
William R. Bryg
Gary N. Hammond
Stephen G. Burger
James O. Hays
Jerome C. Huck
Sunil Saxena
Jonathan K. Ross
Koichi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute for Development of Emerging Architectures Cupertino LLC
Institute for Development of Emerging Architectures LLC
Original Assignee
Institute for Development of Emerging Architectures Cupertino LLC
Institute for Development of Emerging Architectures LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute for Development of Emerging Architectures Cupertino LLC, Institute for Development of Emerging Architectures LLC filed Critical Institute for Development of Emerging Architectures Cupertino LLC
Application granted granted Critical
Publication of DE60003273D1 publication Critical patent/DE60003273D1/de
Publication of DE60003273T2 publication Critical patent/DE60003273T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
DE60003273T 1999-10-31 2000-10-30 Verfahren und Vorrichtung zur Erzeugung einer Eingabeadresse Expired - Lifetime DE60003273T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/430,793 US6393544B1 (en) 1999-10-31 1999-10-31 Method and apparatus for calculating a page table index from a virtual address
US430793 1999-10-31

Publications (2)

Publication Number Publication Date
DE60003273D1 DE60003273D1 (de) 2003-07-17
DE60003273T2 true DE60003273T2 (de) 2004-05-06

Family

ID=23709057

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60003273T Expired - Lifetime DE60003273T2 (de) 1999-10-31 2000-10-30 Verfahren und Vorrichtung zur Erzeugung einer Eingabeadresse

Country Status (5)

Country Link
US (1) US6393544B1 (enExample)
EP (1) EP1096385B1 (enExample)
JP (1) JP4268332B2 (enExample)
CN (1) CN1186729C (enExample)
DE (1) DE60003273T2 (enExample)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6725366B1 (en) * 2000-09-07 2004-04-20 International Business Machines, Corporation System and method for 32 bit code branching to 64 bit targets
US6947970B2 (en) * 2000-12-19 2005-09-20 Intel Corporation Method and apparatus for multilevel translation and protection table
US6671791B1 (en) * 2001-06-15 2003-12-30 Advanced Micro Devices, Inc. Processor including a translation unit for selectively translating virtual addresses of different sizes using a plurality of paging tables and mapping mechanisms
US6807616B1 (en) * 2001-08-09 2004-10-19 Advanced Micro Devices, Inc. Memory address checking in a proccesor that support both a segmented and a unsegmented address space
US6934796B1 (en) * 2002-02-01 2005-08-23 Netlogic Microsystems, Inc. Content addressable memory with hashing function
US6697276B1 (en) 2002-02-01 2004-02-24 Netlogic Microsystems, Inc. Content addressable memory device
US7382637B1 (en) 2002-02-01 2008-06-03 Netlogic Microsystems, Inc. Block-writable content addressable memory device
US7937554B2 (en) 2002-11-12 2011-05-03 Broadcom Corporation System and method for managing memory
KR20040046465A (ko) * 2002-11-27 2004-06-05 한국전자통신연구원 다단계 해시함수를 이용하여 검색시간 한계를 보장하는분리 체이닝 구조의 데이터 처리 시스템 및 그 처리방법
US7093099B2 (en) * 2002-12-12 2006-08-15 Alacritech, Inc. Native lookup instruction for file-access processor searching a three-level lookup cache for variable-length keys
US7143272B2 (en) * 2002-12-27 2006-11-28 Intel Corporation Using computation histories to make predictions
US7069268B1 (en) 2003-01-13 2006-06-27 Cisco Technology, Inc. System and method for identifying data using parallel hashing
US6983355B2 (en) * 2003-06-09 2006-01-03 International Business Machines Corporation Virtualization of physical storage using size optimized hierarchical tables
US7581010B2 (en) * 2003-07-14 2009-08-25 Microsoft Corporation Virtual connectivity with local connection translation
US7509473B2 (en) * 2003-08-27 2009-03-24 Adaptec, Inc. Segmented storage system mapping
US7720930B2 (en) * 2003-12-30 2010-05-18 Intel Corporation Systems and methods using NIC-based prefetching for host TCP context lookup
US7272654B1 (en) * 2004-03-04 2007-09-18 Sandbox Networks, Inc. Virtualizing network-attached-storage (NAS) with a compact table that stores lossy hashes of file names and parent handles rather than full names
US7266670B2 (en) * 2004-06-04 2007-09-04 Faraday Technology Corp. Method of determining whether a virtual address corresponds to a physical address in a translation lookaside buffer
US20060090034A1 (en) * 2004-10-22 2006-04-27 Fujitsu Limited System and method for providing a way memoization in a processing environment
US7685400B2 (en) * 2004-12-15 2010-03-23 International Business Machines Corporation Storage of data blocks of logical volumes in a virtual disk storage subsystem
US7886126B2 (en) * 2005-01-14 2011-02-08 Intel Corporation Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system
JP4573710B2 (ja) * 2005-06-16 2010-11-04 日本電信電話株式会社 データベース管理装置、データベース管理方法及びデータベース管理プログラム
US7657725B2 (en) * 2005-06-24 2010-02-02 Sigmatel, Inc. Integrated circuit with memory-less page table
FR2902208B1 (fr) * 2006-06-12 2009-07-17 Touret Richard Procede de structuration polymorphe et systemique de la memoire associative via un gestionnaire tiers
US20080021865A1 (en) * 2006-07-20 2008-01-24 International Business Machines Corporation Method, system, and computer program product for dynamically determining data placement
US7555628B2 (en) 2006-08-15 2009-06-30 Intel Corporation Synchronizing a translation lookaside buffer to an extended paging table
US9690790B2 (en) 2007-03-05 2017-06-27 Dell Software Inc. Method and apparatus for efficiently merging, storing and retrieving incremental data
CN101645043B (zh) * 2009-09-08 2012-01-04 成都市华为赛门铁克科技有限公司 写数据的方法、读数据的方法及存储设备
US8473684B2 (en) * 2009-12-22 2013-06-25 International Business Machines Corporation Delayed replacement of cache entries
US8862859B2 (en) * 2010-05-07 2014-10-14 International Business Machines Corporation Efficient support of multiple page size segments
US8745307B2 (en) 2010-05-13 2014-06-03 International Business Machines Corporation Multiple page size segment encoding
US8478740B2 (en) * 2010-12-16 2013-07-02 Microsoft Corporation Deriving document similarity indices
US9141523B2 (en) * 2011-02-25 2015-09-22 Mitsubishi Electric Corporation Control apparatus, control system, and communication method for controlling one or more motors in serial communication with a controller
GB2498571A (en) 2012-01-20 2013-07-24 Intellectual Ventures Holding 81 Llc Base station able to communicate with a second device type on a narrow subset frequency band contained within a first main band
US9058268B1 (en) 2012-09-20 2015-06-16 Matrox Graphics Inc. Apparatus, system and method for memory management
US9355032B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Supporting multiple types of guests by a hypervisor
US9355040B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Adjunct component to provide full virtualization using paravirtualized hypervisors
US9600419B2 (en) 2012-10-08 2017-03-21 International Business Machines Corporation Selectable address translation mechanisms
US9740624B2 (en) 2012-10-08 2017-08-22 International Business Machines Corporation Selectable address translation mechanisms within a partition
US9348757B2 (en) 2012-10-08 2016-05-24 International Business Machines Corporation System supporting multiple partitions with differing translation formats
US9280488B2 (en) 2012-10-08 2016-03-08 International Business Machines Corporation Asymmetric co-existent address translation structure formats
US10216642B2 (en) * 2013-03-15 2019-02-26 International Business Machines Corporation Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size
CN103942161B (zh) * 2014-04-24 2017-02-15 杭州冰特科技有限公司 只读缓存的去冗余系统及方法以及缓存的去冗余方法
JP6406283B2 (ja) * 2016-03-01 2018-10-17 日本電気株式会社 ストレージ装置およびストレージ方法
US10528353B2 (en) 2016-05-24 2020-01-07 International Business Machines Corporation Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor
US10248555B2 (en) 2016-05-31 2019-04-02 International Business Machines Corporation Managing an effective address table in a multi-slice processor
US10467008B2 (en) 2016-05-31 2019-11-05 International Business Machines Corporation Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor
US11341058B2 (en) * 2018-07-26 2022-05-24 Vmware Inc. Handling software page faults using data from hierarchical data structures
US20200073822A1 (en) * 2018-08-30 2020-03-05 Micron Technology, Inc. Security Configuration for Memory Address Translation from Object Specific Virtual Address Spaces to a Physical Address Space
US11182507B2 (en) 2018-08-30 2021-11-23 Micron Technology, Inc. Domain crossing in executing instructions in computer processors
US11481241B2 (en) 2018-08-30 2022-10-25 Micron Technology, Inc. Virtual machine register in a computer processor
US11914726B2 (en) 2018-08-30 2024-02-27 Micron Technology, Inc. Access control for processor registers based on execution domains
US11500665B2 (en) 2018-08-30 2022-11-15 Micron Technology, Inc. Dynamic configuration of a computer processor based on the presence of a hypervisor
US10942863B2 (en) 2018-08-30 2021-03-09 Micron Technology, Inc. Security configurations in page table entries for execution domains using a sandbox application operation
US11544069B2 (en) 2018-10-25 2023-01-03 Micron Technology, Inc. Universal pointers for data exchange in a computer system having independent processors
CN110365806B (zh) * 2019-06-06 2022-05-10 无线生活（杭州）信息科技有限公司 网址转换方法及装置
CN113726661B (zh) * 2021-08-27 2022-10-18 西安微电子技术研究所 一种高性能低功耗的路由哈希器及其控制方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5649142A (en) * 1991-10-24 1997-07-15 Intel Corporation Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault
US5826057A (en) * 1992-01-16 1998-10-20 Kabushiki Kaisha Toshiba Method for managing virtual address space at improved space utilization efficiency
US5555387A (en) * 1995-06-06 1996-09-10 International Business Machines Corporation Method and apparatus for implementing virtual memory having multiple selected page sizes
DE4410060B4 (de) 1993-04-08 2006-02-09 Hewlett-Packard Development Co., L.P., Houston Übersetzungsvorrichtung zum Umsetzen einer virtuellen Speicheradresse in eine physikalische Speicheradresse
US5630087A (en) * 1994-11-02 1997-05-13 Sun Microsystems, Inc. Apparatus and method for efficient sharing of virtual memory translations
US6079004A (en) * 1995-01-27 2000-06-20 International Business Machines Corp. Method of indexing a TLB using a routing code in a virtual address
US5946716A (en) * 1996-05-30 1999-08-31 Hewlett-Packard Company Sectored virtual memory management system and translation look-aside buffer (TLB) for the same
AUPO194696A0 (en) * 1996-08-28 1996-09-19 Canon Information Systems Research Australia Pty Ltd A method of efficiently updating hashed page tables
US5809563A (en) * 1996-11-12 1998-09-15 Institute For The Development Of Emerging Architectures, Llc Method and apparatus utilizing a region based page table walk bit
US5918251A (en) * 1996-12-23 1999-06-29 Intel Corporation Method and apparatus for preloading different default address translation attributes
US6012132A (en) * 1997-03-31 2000-01-04 Intel Corporation Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table
US6088780A (en) * 1997-03-31 2000-07-11 Institute For The Development Of Emerging Architecture, L.L.C. Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address
US6557121B1 (en) 1997-03-31 2003-04-29 International Business Machines Corporation Method and system for fault isolation for PCI bus errors

Also Published As

Publication number Publication date
US6393544B1 (en) 2002-05-21
EP1096385B1 (en) 2003-06-11
JP4268332B2 (ja) 2009-05-27
EP1096385A1 (en) 2001-05-02
JP2001175536A (ja) 2001-06-29
CN1296224A (zh) 2001-05-23
DE60003273D1 (de) 2003-07-17
CN1186729C (zh) 2005-01-26

Similar Documents

Publication Publication Date Title
DE60003273T2 (de) Verfahren und Vorrichtung zur Erzeugung einer Eingabeadresse
DE4410060B4 (de) Übersetzungsvorrichtung zum Umsetzen einer virtuellen Speicheradresse in eine physikalische Speicheradresse
DE69427625T2 (de) Adressübersetzungsmechanismus für Rechnersystem mit virtuellen Speicher, der eine Vielzahl von Seitengrössen unterstützt
DE60036960T2 (de) Unterscheidung von feinkorntranslation
DE69424767T2 (de) Kohärente Schreibtransaktionen für Teilzeilen eines Cache-Speichers
DE68923863T2 (de) Ein-/Ausgabecachespeicherung.
DE69814579T2 (de) Parallel arbeitende exklusiv-oder-einheit
DE69732181T2 (de) Verfahren und gerät zum zwischenspeichern von systemverwaltungsinformationen mit anderen informationen
DE69721590T2 (de) Ein bereichsbasiertes seiten-table-walk-bit verwendendes verfahren sowie vorrichtung
DE69637294T2 (de) Mikro-tlb mit parallelem zugriff zum beschleunigen der adressübersetzung
DE3805107C2 (enExample)
DE60320026T2 (de) Verbessertes speichermanagement für echtzeit-anwendungen
DE69513126T2 (de) Verfahren und Gerät zum schnellen Vergleichen für Adressen eines Pufferspeichers mit Fehlerkorrektur
DE69229667T2 (de) Simulierte cachespeicher-assoziativität
DE69031411T2 (de) Verfahren und Anordnung zum Lesen, Schreiben und Auffrischen eines Speichers mit direktem virtuellem oder physikalischem Zugriff
DE69033064T2 (de) Verfahren zur Zuordnung von reellen Seiten zu virtuellen Seiten mit davon verschiedenen Seitengrössen
DE69230211T2 (de) Integrierter Speicher, Verwaltungsverfahren und resultierendes Informationssystem
DE69231611T2 (de) Verfahren zu grosser logischer Adressierung
DE3932675A1 (de) Virtuelles maschinensystem
DE2459006A1 (de) Verfahren und einrichtung zur entwicklung absoluter adressen bei segmentadressierung
DE10002120A1 (de) Logikstruktur eines Adressumsetzpuffers
DE69130942T2 (de) Vorrichtung zur Erhöhung der Leistung eines Adressenübersetzungspuffers
DE69623691T2 (de) Ein Gerät und Verfahren, das ein für Cache-Kollisionen weniger anfälliges Cache-Indizierungsverfahren vorsieht
DE69030072T2 (de) Schneller Durchschreib-Cache-Speicher
DE4234695C2 (de) Computer-Speichersystem und Verfahren zur Aufrechterhaltung der Cache-Kohärenz zwischen einem Daten-Cache und einem Segmentdeskriptor-Cache

Legal Events

Date Code Title Description
8364 No opposition during term of opposition