DE60002453D1 - Dominologoik mit einer versorgungsspannung für einen vierphasentakt - Google Patents

Dominologoik mit einer versorgungsspannung für einen vierphasentakt

Info

Publication number
DE60002453D1
DE60002453D1 DE60002453T DE60002453T DE60002453D1 DE 60002453 D1 DE60002453 D1 DE 60002453D1 DE 60002453 T DE60002453 T DE 60002453T DE 60002453 T DE60002453 T DE 60002453T DE 60002453 D1 DE60002453 D1 DE 60002453D1
Authority
DE
Germany
Prior art keywords
dominologoics
supply voltage
phase clock
clock
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60002453T
Other languages
English (en)
Inventor
Saleh Abdel-Hafeez
Nalini Ranjan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S3 Inc
Original Assignee
S3 Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S3 Inc filed Critical S3 Inc
Application granted granted Critical
Publication of DE60002453D1 publication Critical patent/DE60002453D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE60002453T 1999-06-04 2000-06-05 Dominologoik mit einer versorgungsspannung für einen vierphasentakt Expired - Lifetime DE60002453D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/326,161 US6265899B1 (en) 1999-06-04 1999-06-04 Single rail domino logic for four-phase clocking scheme
PCT/US2000/015533 WO2000076068A2 (en) 1999-06-04 2000-06-05 Single rail domino logic for four-phase clocking scheme

Publications (1)

Publication Number Publication Date
DE60002453D1 true DE60002453D1 (de) 2003-06-05

Family

ID=23271058

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60002453T Expired - Lifetime DE60002453D1 (de) 1999-06-04 2000-06-05 Dominologoik mit einer versorgungsspannung für einen vierphasentakt

Country Status (6)

Country Link
US (1) US6265899B1 (de)
EP (1) EP1166443B1 (de)
JP (1) JP2003501935A (de)
CA (1) CA2338114C (de)
DE (1) DE60002453D1 (de)
WO (1) WO2000076068A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
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US20040019923A1 (en) * 1997-10-16 2004-01-29 Ivarie Robert D. Exogenous proteins expressed in avians and their eggs
US6441648B1 (en) * 2001-05-09 2002-08-27 Intel Corporation Double data rate dynamic logic
US7187209B2 (en) * 2003-08-13 2007-03-06 Via Technologies, Inc. Non-inverting domino register
US7187211B2 (en) * 2002-08-14 2007-03-06 Via Technologies, Inc. P-domino output latch
US7417465B2 (en) * 2002-08-14 2008-08-26 Via Technologies, Inc. N-domino output latch
US7193445B2 (en) * 2002-08-14 2007-03-20 Ip-First, Llc Non-inverting domino register
US7123056B2 (en) * 2002-12-09 2006-10-17 Mosaid Technologies Incorporated Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines
US7095400B2 (en) * 2003-07-28 2006-08-22 Inventec Appliances Corp. Method of automatically enabling or disabling backlight of electronic device based on a predetermined time
TWI237265B (en) * 2003-08-13 2005-08-01 Ip First Llc Non-inverting domino register
US7187210B2 (en) * 2003-08-13 2007-03-06 Via Technologies, Inc. P-domino register
US9679602B2 (en) 2006-06-14 2017-06-13 Seagate Technology Llc Disc drive circuitry swap
US7321243B1 (en) * 2006-06-16 2008-01-22 Via Technologies, Inc. P-domino register with accelerated non-charge path
US7317339B1 (en) * 2006-06-16 2008-01-08 Via Technologies, Inc. N-domino register with accelerated non-discharge path
US7348806B2 (en) 2006-08-11 2008-03-25 Via Technologies, Inc. Accelerated N-channel dynamic register
US7382161B2 (en) * 2006-08-11 2008-06-03 Via Technologies, Inc. Accelerated P-channel dynamic register
US9305590B2 (en) 2007-10-16 2016-04-05 Seagate Technology Llc Prevent data storage device circuitry swap
US7990180B2 (en) * 2009-09-09 2011-08-02 Via Technologies, Inc. Fast dynamic register
KR101911060B1 (ko) 2012-03-19 2018-10-23 삼성전자주식회사 푸터가 없는 ｎｐ 도미노 로직 회로와 이를 포함하는 장치들
KR101908409B1 (ko) * 2012-04-02 2018-10-17 삼성전자 주식회사 클럭 지연 도미노 로직 회로 및 이를 포함하는 장치들
US8860463B1 (en) 2013-04-24 2014-10-14 Via Technologies, Inc. Fast dynamic register with transparent latch
US9742408B1 (en) * 2016-09-23 2017-08-22 International Business Machines Corporation Dynamic decode circuit with active glitch control
US10374604B1 (en) 2018-08-12 2019-08-06 International Business Machines Corporation Dynamic decode circuit low power application
KR102557751B1 (ko) * 2020-07-15 2023-07-24 한양대학교 산학협력단 단일 극성 다이나믹 로직 회로

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700086A (en) 1985-04-23 1987-10-13 International Business Machines Corporation Consistent precharge circuit for cascode voltage switch logic
FR2596595B1 (fr) 1986-03-28 1988-05-13 Radiotechnique Compelec Porte logique mos du type domino
US5208489A (en) 1986-09-03 1993-05-04 Texas Instruments Incorporated Multiple compound domino logic circuit
US5015882A (en) 1986-09-03 1991-05-14 Texas Instruments Incorporated Compound domino CMOS circuit
US4985643A (en) 1988-06-24 1991-01-15 National Semiconductor Corporation Speed enhancement technique for CMOS circuits
US4896057A (en) 1988-09-14 1990-01-23 United States Of America As Represented By The Administrator, National Aeronautics And Space Administration High-speed dynamic domino circuit implemented with gaas mesfets
US5041742A (en) 1990-05-09 1991-08-20 Motorola, Inc. Structured scan path circuit for incorporating domino logic
US5121003A (en) 1990-10-10 1992-06-09 Hal Computer Systems, Inc. Zero overhead self-timed iterative logic
US5208490A (en) 1991-04-12 1993-05-04 Hewlett-Packard Company Functionally complete family of self-timed dynamic logic circuits
US5263173A (en) * 1991-07-10 1993-11-16 Hewlett-Packard Company High speed clocked output driver for switching logic levels of an output pad at integer and integer and a half clock cycles
US5146115A (en) 1991-07-26 1992-09-08 Zilog, Inc. Domino-logic decoder
US5369651A (en) 1992-06-30 1994-11-29 Intel Corporation Multiplexed byte enable bus for partial word writes to ECC protected memory
US5402012A (en) 1993-04-19 1995-03-28 Vlsi Technology, Inc. Sequentially clocked domino-logic cells
US5453708A (en) 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5541536A (en) 1995-03-01 1996-07-30 Sun Microsystems, Inc. Rubberband logic
US5517136A (en) 1995-03-03 1996-05-14 Intel Corporation Opportunistic time-borrowing domino logic
US5661675A (en) 1995-03-31 1997-08-26 Intel Corporation Positive feedback circuit for fast domino logic
US5642061A (en) 1995-04-17 1997-06-24 Hitachi America, Ltd. Short circuit current free dynamic logic clock timing
US5550490A (en) 1995-05-25 1996-08-27 International Business Machines Corporation Single-rail self-resetting logic circuitry
US5565798A (en) 1995-08-21 1996-10-15 International Business Machines Corporation Self-timed control circuit for self-resetting logic circuitry
US5712578A (en) 1995-12-27 1998-01-27 Intel Corporation PLA architecture having improved clock signal to output timing using a type-I domino and plane
US5825208A (en) * 1996-05-20 1998-10-20 International Business Machines Corporation Method and apparatus for fast evaluation of dynamic CMOS logic circuits
US5821778A (en) * 1996-07-19 1998-10-13 Texas Instruments Incorporated Using cascode transistors having low threshold voltages
US5796282A (en) 1996-08-12 1998-08-18 Intel Corporation Latching mechanism for pulsed domino logic with inherent race margin and time borrowing
KR20000069742A (ko) 1996-12-27 2000-11-25 피터 엔. 데트킨 처음과 마지막 스테이지에는 클록을 그리고 마지막 스테이지에는 래치를 구비한 단일-위상 도미노 시간 빌림 논리
US6040716A (en) * 1997-05-19 2000-03-21 Texas Instruments Incorporated Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage
TW344131B (en) * 1997-06-03 1998-11-01 Nat Science Council A 1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined

Also Published As

Publication number Publication date
US6265899B1 (en) 2001-07-24
EP1166443A2 (de) 2002-01-02
WO2000076068A2 (en) 2000-12-14
EP1166443B1 (de) 2003-05-02
EP1166443A4 (de) 2002-01-02
CA2338114C (en) 2003-04-15
CA2338114A1 (en) 2000-12-14
WO2000076068A3 (en) 2001-10-11
JP2003501935A (ja) 2003-01-14

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Legal Events

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