DE60002397D1 - Schneller verkettenbarer volladdierer mit differentiellen eingängen - Google Patents
Schneller verkettenbarer volladdierer mit differentiellen eingängenInfo
- Publication number
- DE60002397D1 DE60002397D1 DE60002397T DE60002397T DE60002397D1 DE 60002397 D1 DE60002397 D1 DE 60002397D1 DE 60002397 T DE60002397 T DE 60002397T DE 60002397 T DE60002397 T DE 60002397T DE 60002397 D1 DE60002397 D1 DE 60002397D1
- Authority
- DE
- Germany
- Prior art keywords
- chainable
- faster
- full adder
- differential inputs
- differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/5013—Half or full adders, i.e. basic adder cells for one denomination using algebraic addition of the input signals, e.g. Kirchhoff adders
Landscapes
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9901179A FR2789192B1 (fr) | 1999-02-02 | 1999-02-02 | Additionneur chainable rapide a retenue anticipee |
FR9901179 | 1999-05-18 | ||
PCT/FR2000/000242 WO2000046663A1 (fr) | 1999-02-02 | 2000-02-02 | Additionneur complet chainable rapide |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60002397D1 true DE60002397D1 (de) | 2003-06-05 |
DE60002397T2 DE60002397T2 (de) | 2004-04-01 |
Family
ID=9541504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60002397T Expired - Lifetime DE60002397T2 (de) | 1999-02-02 | 2000-02-02 | Schneller verkettenbarer volladdierer mit differentiellen eingängen |
Country Status (5)
Country | Link |
---|---|
US (1) | US6658446B1 (de) |
EP (1) | EP1066557B1 (de) |
DE (1) | DE60002397T2 (de) |
FR (1) | FR2789192B1 (de) |
WO (1) | WO2000046663A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010056455A1 (en) * | 2000-03-17 | 2001-12-27 | Rong Lin | Family of low power, regularly structured multipliers and matrix multipliers |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3093751A (en) * | 1959-08-14 | 1963-06-11 | Sperry Rand Corp | Logical circuits |
US3900724A (en) * | 1974-02-11 | 1975-08-19 | Trw Inc | Asynchronous binary multiplier using non-threshold logic |
US4133040A (en) * | 1977-06-30 | 1979-01-02 | Rca Corporation | Multi-function logic gate with one gate delay |
JPS60247734A (ja) * | 1984-05-24 | 1985-12-07 | Toshiba Corp | 論理演算回路 |
EP0344226B1 (de) * | 1987-08-25 | 1993-05-05 | Hughes Aircraft Company | Anordnung zur schnellen addition von binärzahlen |
JP2607538B2 (ja) * | 1987-08-28 | 1997-05-07 | 株式会社日立製作所 | 加算回路 |
US5175703A (en) * | 1991-04-29 | 1992-12-29 | Motorola, Inc. | High speed full adder and method |
US5499203A (en) * | 1992-09-27 | 1996-03-12 | Grundland; Nathan | Logic elements for interlaced carry/borrow systems having a uniform layout |
FR2699025B1 (fr) | 1992-12-04 | 1995-01-06 | Thomson Csf Semiconducteurs | Convertisseur analogique numérique. |
FR2700084B1 (fr) | 1992-12-30 | 1995-02-10 | Thomson Csf Semiconducteurs | Convertisseur analogique numérique avec échantillonneur bloqueur distribué. |
JP3110221B2 (ja) * | 1993-10-04 | 2000-11-20 | 株式会社東芝 | 全加算器回路 |
US5487025A (en) * | 1993-11-15 | 1996-01-23 | Intergraph Corporation | Carry chain adder using regenerative push-pull differential logic |
JP3330236B2 (ja) * | 1994-09-01 | 2002-09-30 | 三菱電機エンジニアリング株式会社 | 加算回路およびキャリー選択回路 |
FR2750549B1 (fr) | 1996-06-28 | 1998-09-18 | Thomson Csf | Convertisseur analogique-numerique |
-
1999
- 1999-02-02 FR FR9901179A patent/FR2789192B1/fr not_active Expired - Fee Related
-
2000
- 2000-02-02 WO PCT/FR2000/000242 patent/WO2000046663A1/fr active IP Right Grant
- 2000-02-02 DE DE60002397T patent/DE60002397T2/de not_active Expired - Lifetime
- 2000-02-02 US US09/647,537 patent/US6658446B1/en not_active Expired - Fee Related
- 2000-02-02 EP EP00901700A patent/EP1066557B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO2000046663A1 (fr) | 2000-08-10 |
FR2789192B1 (fr) | 2001-04-20 |
FR2789192A1 (fr) | 2000-08-04 |
EP1066557B1 (de) | 2003-05-02 |
EP1066557A1 (de) | 2001-01-10 |
DE60002397T2 (de) | 2004-04-01 |
US6658446B1 (en) | 2003-12-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |