DE60000666D1 - Integrierte schaltkreisanordnung welche gegen angriffe durch kontrollierte zerstörung einer komplementären schicht gesichert ist - Google Patents

Integrierte schaltkreisanordnung welche gegen angriffe durch kontrollierte zerstörung einer komplementären schicht gesichert ist

Info

Publication number
DE60000666D1
DE60000666D1 DE60000666T DE60000666T DE60000666D1 DE 60000666 D1 DE60000666 D1 DE 60000666D1 DE 60000666 T DE60000666 T DE 60000666T DE 60000666 T DE60000666 T DE 60000666T DE 60000666 D1 DE60000666 D1 DE 60000666D1
Authority
DE
Germany
Prior art keywords
film
integrated circuit
active
circuit arrangement
secured against
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE60000666T
Other languages
English (en)
Other versions
DE60000666T2 (de
Inventor
Beatrice Bonvalot
Robert Leydier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Axalto SA
Original Assignee
Schlumberger Systemes SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=9544592&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60000666(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Schlumberger Systemes SA filed Critical Schlumberger Systemes SA
Publication of DE60000666D1 publication Critical patent/DE60000666D1/de
Application granted granted Critical
Publication of DE60000666T2 publication Critical patent/DE60000666T2/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Credit Cards Or The Like (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Thin Film Transistor (AREA)
DE60000666T 1999-04-19 2000-04-19 Integrierte schaltkreisanordnung welche gegen angriffe durch kontrollierte zerstörung einer komplementären schicht gesichert ist Revoked DE60000666T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9904916A FR2792440B1 (fr) 1999-04-19 1999-04-19 Dispositif a circuit integre securise contre des attaques procedant par destruction controlee d'une couche complementaire
PCT/FR2000/001031 WO2000063836A1 (fr) 1999-04-19 2000-04-19 Dispositif a circuit integre securise contre des attaques procedant par destruction controlee d'une couche complementaire

Publications (2)

Publication Number Publication Date
DE60000666D1 true DE60000666D1 (de) 2002-11-28
DE60000666T2 DE60000666T2 (de) 2003-07-03

Family

ID=9544592

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60000666T Revoked DE60000666T2 (de) 1999-04-19 2000-04-19 Integrierte schaltkreisanordnung welche gegen angriffe durch kontrollierte zerstörung einer komplementären schicht gesichert ist

Country Status (9)

Country Link
US (1) US6576991B1 (de)
EP (1) EP1183642B1 (de)
JP (1) JP4566412B2 (de)
CN (1) CN1184594C (de)
AT (1) ATE226744T1 (de)
DE (1) DE60000666T2 (de)
ES (1) ES2185588T3 (de)
FR (1) FR2792440B1 (de)
WO (1) WO2000063836A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10029035C1 (de) * 2000-06-13 2002-02-28 Infineon Technologies Ag Verfahren zur Bearbeitung eines Wafers
FR2828334A1 (fr) * 2001-08-03 2003-02-07 Schlumberger Systems & Service Procede pour rendre connectable electriquement et mecaniquement un dispositif electrique ayant une face munie de plots de contacts
DE60333739D1 (de) * 2002-03-21 2010-09-23 Nxp Bv Halbleiterbauelement mit einer schutzenden sicherheitsbeschichtung und verfahren zu seiner herstellung
EP1540729A1 (de) * 2002-09-17 2005-06-15 Axalto SA Verfahren zur herstellung einer wafer-baugruppe
US20050263596A1 (en) * 2004-05-12 2005-12-01 Solicore, Inc. Portable charger, including portable sleeve, for an electronically readable card
JP4581011B2 (ja) * 2008-01-25 2010-11-17 株式会社東芝 電気部品とその製造方法
FR2935061A1 (fr) * 2008-08-13 2010-02-19 St Microelectronics Rousset Dispositif de detection d'une attaque d'un circuit integre
JP5466102B2 (ja) * 2010-07-08 2014-04-09 セイコーインスツル株式会社 貫通電極付きガラス基板の製造方法及び電子部品の製造方法
CN117923411A (zh) * 2024-03-25 2024-04-26 成都凯天电子股份有限公司 一种碳化硅电容式压力传感器及其制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2517165A1 (fr) * 1981-11-20 1983-05-27 Radiotechnique Compelec Procede pour munir d'un ecran un circuit electronique, et carte de paiement munie d'un ecran
FR2677785A1 (fr) * 1991-06-17 1992-12-18 Philips Composants Procede de fabrication d'une carte a microcircuit.
US5468990A (en) * 1993-07-22 1995-11-21 National Semiconductor Corp. Structures for preventing reverse engineering of integrated circuits
US5581445A (en) * 1994-02-14 1996-12-03 Us3, Inc. Plastic integrated circuit card with reinforcement structure for protecting integrated circuit module
FR2727227B1 (fr) * 1994-11-17 1996-12-20 Schlumberger Ind Sa Dispositif de securite actif a memoire electronique
JPH08213392A (ja) * 1995-02-01 1996-08-20 Oki Electric Ind Co Ltd 半導体素子及びその製造方法
JP2905736B2 (ja) * 1995-12-18 1999-06-14 株式会社エイ・ティ・アール光電波通信研究所 半導体装置
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5898215A (en) * 1996-12-16 1999-04-27 Motorola, Inc. Microelectronic assembly with connection to a buried electrical element, and method for forming same
FR2767966B1 (fr) * 1997-08-28 1999-12-03 Schlumberger Ind Sa Dispositif a circuit integre securise et procede de fabrication
DE19741889C2 (de) * 1997-09-23 2000-06-08 Hoeft & Wessel Aktiengesellsch Baugruppe mit einem Datenspeicher und einem Beschädigungsdetektor
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
JP2000186931A (ja) * 1998-12-21 2000-07-04 Murata Mfg Co Ltd 小型電子部品及びその製造方法並びに該小型電子部品に用いるビアホールの成形方法
US6326698B1 (en) * 2000-06-08 2001-12-04 Micron Technology, Inc. Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices

Also Published As

Publication number Publication date
ATE226744T1 (de) 2002-11-15
ES2185588T3 (es) 2003-05-01
CN1184594C (zh) 2005-01-12
EP1183642A1 (de) 2002-03-06
US6576991B1 (en) 2003-06-10
FR2792440B1 (fr) 2001-06-08
JP4566412B2 (ja) 2010-10-20
WO2000063836A1 (fr) 2000-10-26
FR2792440A1 (fr) 2000-10-20
DE60000666T2 (de) 2003-07-03
CN1347535A (zh) 2002-05-01
EP1183642B1 (de) 2002-10-23
JP2003521757A (ja) 2003-07-15

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8327 Change in the person/name/address of the patent owner

Owner name: AXALTO S.A., MONTROUGE, FR

8331 Complete revocation