DE4101274A1 - SEMICONDUCTOR COMPONENT HIGH RELIABILITY - Google Patents

Description

The invention relates to a high semiconductor device Reliability according to the preamble of claim 1.

An integrated circuit using CMOS technology is more common have a number of advantages, such as high ones Noise immunity and low power consumption. Dementspre The trend in the design of DRAM components is corresponding from NMOS technology to CMOS technology, which is the pre partly higher packing density and further miniaturization brings with it. At the same time, it will depend on it continuously works, the component from deteriorating its egg properties due to the latch-up effect and the electrostatic Protect the defect (ESD), causing inherent difficulties a CMOS circuit. Especially the electrostatic Defect caused by discharge of frictional electricity that arises between two materials, such as. B. between different plastic materials or between clothes and the human body, the CMOS integrated circuit can destroy and reduce the reliability of the component. This is the main cause of the electrostatic breakthrough Breakdown phenomenon of a gate oxide layer due to the on one Static electricity input known. The through  The gate oxide layer has traditionally been broken Add a protection circuit with a resistor, one Prevents diode and the like in the gate input stage. As is a second cause of electrostatic breakthrough a junction breakdown of elements of an output stage due to the static electricity present on the output side known.

The junction breakdown of the elements in the output stage by static electricity is explained in detail below with reference to FIG. 1. In a known ESD tolerance test according to FIG. 1, an ESD test arrangement ( 2 ) is connected between an output (OT) and a ground connection (Vss) of a chip ( 1 ). The ESD test arrangement ( 2 ) can be represented by a series equivalent circuit of a switch (SW), a resistor (RT) and a capacitor (CT). The ESD test is carried out as follows. First, the capacitor (CT) is charged to several 100 to several 1000 volts. Then the switch (SW) is short-circuited, after which the static electricity charged in the capacitor (CT) is discharged via the chip ( 1 ) and the extent of the resulting defect in the chip ( 1 ) is checked. The discharge current (Io) during the test flows to ground via a pull-down transistor (M 2 ) in the output stage.

If the voltage of the charged capacitor (CT) is positive, an np drain junction ( 15 a) of the pull-down transistor (M 2 ) shown in FIG. 2 in the reverse direction and an np source junction ( 15 b) of the transistor (M 2 ) polarized in the forward direction, so that the breakdown in the np drain junction ( 15 a) occurs due to the high voltage supplied to a metallic drain wiring layer ( 16 b) and at the same time the discharge current (Io) from the drain junction ( 15 a) to the source junction ( 15 b) flows. When the switch (SW) is open, the electrostatic energy (E) stored in the capacitor (CT) with a capacitance of 100 pF, provided that the charging voltage of the capacitor (CT) is 2000 V, is determined by the following equations:

There is therefore an energy of 0.2 mJ charged and stored in the capacitor (CT) via the resistor (RT) of the ESD test arrangement ( 2 ) and the pull-down transistor (M 2 ) of the output stage of the chip ( 1 ) consumed. If the resistance of the element of the output stage is small, the discharge time can be written as follows:

τ = RT · CT = 100 pF × 1.5 KΩ = 0.15 µs,

where the value of the resistance (RT) is 1.5 KΩ. The mitt The power loss (W) is therefore as follows:

This means that the total stored energy of 0.2 mJ with a power of approx. 1.3 KW for approx. 0.15µs via the resistance (RT) and the reverse biased np drain transition area ( 15 a) of the pull-down Transistor (M 2 ) of the output stage of the chip is consumed. In the transition area, heat is therefore generated which is proportional to the product of the value of the voltage in the reverse direction (usually 10 V to 30 V) with the discharge current (Io). Due to the heat, the metallic drain electrode layer ( 16 b), which has a low melting point, tends to melt, or there is a short circuit between the metallic drain electrode layer ( 16 b) and the substrate ( 10 ) due to a reaction between the metal and the silicon in Transition to. As a result, the np junction ( 15 a) is destroyed in such a way that the leakage current increases, which worsens the functional properties of the component. By using higher packing density and further miniaturization, the depth of the n⁺ layers ( 15 a and 15 b) in the integrated CMOS circuit was reduced to approximately 0.2 μm to 0.7 μm in order to reduce the short-channel phenomenon. If the depth of a transition surface shorting tip ( 18 ), which occurs in the contact area of the metallic wiring layer ( 16 b) and the silicon substrate ( 10 ) extending into the latter, exceeds the depth of the n⁺ layer, this results in an increase in the Leakage current and a reduction in the transition breakdown voltage cause, which adversely affects the properties of the device and thus deteriorates the reliability.

In a conventional method, a resistor is therefore introduced between the output (OT) and the drain of the pull-down transistor (M 2 ) in order to increase the discharge time constant (τ) and thus reduce the peak current or dissipate the energy consumption. In this case, however, the change in the output voltage is inhibited by the reduced output current due to the inserted resistance, which results in a lower operating speed. Accordingly, an n⁺ interface layer with a resistance of approximately 10Ω and less or a wiring layer with a low resistance, such as, for. B. made of doped poly crystalline silicon or the like. However, due to the above limitations, such as slowing down the operating speed, this does not show the desired effects in terms of protecting the output stage against the ESD effect.

As an alternative, the melting reaction is reported between to prevent the silicon substrate and the metal layer that in between a heavy metal layer  melting metal, such as B. W, Mo, Ti, Ta or Co, on the Contact area is applied, so the resistance to improve the contact area compared to ESD. The ESD tole ranz the transition layer in the transistor of the output stage but is not directly increased by this method.

The invention has for its object a semiconductor device to create high reliability, which is an ESD tolerant Has contact transition structure and so described above overcomes difficulties of the known components.

This task is performed by a semiconductor device with the Merk paint the claim 1 solved.

The flat transition area can be a drain or source area of a transistor, preferably a MOS transistor, serve. Such a transistor can be found in the output stage of a chip.

In a further embodiment of the invention is according to claim 12 a semiconductor device, in particular a CMOS semiconductor device element provided such that a conventional MOS transistor with only a flat transition area between one MOS transistor with a deep transition region that one from Has substrate different charge carrier type, and a ü Lichen MOS transistor in a well in the substrate with it different charge carrier type is formed, is introduced. This can solve the problems such. B. the latch-up effect overcome very effectively.

In a development of the invention, the CMOS semiconductor device ment a deep transition area, in the same process step how the trough is formed in the substrate. The semiconductor component can thus be manufactured very easily are changed by simply changing the layout of the layout without additional manufacturing steps being necessary.

A preferred embodiment of the invention is in the drawing shown and is described below. Show it:

Fig. 1 is an equivalent circuit diagram for the ESD test of an output stage of a known integrated CMOS circuit,

Fig. 2 shows the structure in the region of an output stage section of a known CMOS integrated circuit in cross-,

Fig. 3 shows the structure of a semiconductor device according to the invention high reliability in cross section and

FIGS. 4A to 4K, the respective cross-sectional structure of a fiction, modern CMOS semiconductor device while the other aufein following manufacturing steps.

In the semiconductor component according to the invention shown in FIG. 3 high reliability are flat transition areas ( 22 a and 22 b) of a second conductivity type in a semiconductor substrate ( 20 ) of a first conductivity type in a depth of about 0.2 microns to 0.7 microns and low impedance thereon Wiring layers ( 24 a and 24 b) through contact holes ( 25 a and 25 b) formed in an insulation layer ( 28 ) formed therethrough. In addition to the contact area in the flat transition areas ( 22 a, 22 b), the semiconductor component also has deep transition areas of the second conductivity type ( 26 a, 26 b), which extend to a depth of 3 μm to 6 μm into the semiconductor substrate ( 20 ) . The respective depth of the deep transition areas ( 26 a, 26 b) is determined so that it has a transition short-circuiting tip ( 29 ), which is caused by electrostatic discharge in the contact area of the low-resistance wiring layers ( 24 a, 24 b) and the flat transition areas ( 22 a, 22 b) arises, encloses in a sufficient manner. In the case of an NMOS transistor, the first conductivity type consists of doping atoms of the p-type, the second conductivity type consists of those of the n-type, in the case of a PMOS transistor the reverse. A gate electrode layer ( 23 ) and a field oxide layer ( 27 ) are also provided. Therefore, although a transition short-circuit peak ( 29 ) can occur in the contact area ( 25 b) due to static electricity, this influences and thus the breakdown area of the transition, due to the deep transition area ( 26 b) in this semiconductor component of high reliability not the semiconductor substrate ( 20 ) of the first conductivity type.

The deep transition region below the contact region can be designed in such a way that the deep n⁺ or p⁺ transition region is formed within the flat transition region, in that phosphorus or boron ions are only rich in the contact region using the thicknesses formed around the contact holes Insulation layer ( 28 ) are implanted as a mask after the contact holes ( 25 a, 25 b) have been created. However, this requires an additional ion implantation step and two photolithographic processes to implant n separat or p bzw. doping atoms separately. In addition, since the element already formed with the contact area cannot withstand a high-temperature tempering process, the activation of the P⁺ or B⁺ ions implanted in the contact area cannot be achieved in a simple manner.

Therefore, a method is used to produce the CMOS semiconductor device according to the invention with high reliability, which is illustrated in FIGS . 4A to 4K. Here, when the formation of the well of the second conductivity type is carried out in the usual manufacturing step of the CMOS semiconductor device, the deep transition region below the contact region is simultaneously formed, so that the above-described inadequacies of the known manufacturing method are compensated for and the ESD tolerance of the Transistor of the output stage is enlarged.

FIGS. 4A to 4K show the method in the case where a twin-well CMOS process are used for a substrate of p-type and n⁺-doped polycrystalline silicon gate.

Fig. 4A shows a by thermal growth in an oxidate gas atmosphere at 1000 ° C in an oriented in 100-direction Si liziumsubstratkristall (100) having a resistivity of about 10 Ω cm at a thickness of about 30 nm applied pad oxide layer (101) . An Si ₃ N ₄ nitride layer ( 102 ) is deposited on the oxide layer ( 101 ) in a thickness of approximately 10 nm by means of a CVD process. Thereafter, the nitride layer ( 102 ) in the region of the n-well regions ( 104 a, 104 b and 105 ) described later in connection with FIG. 4C are removed by a conventional photoetching method and phosphorus ions (P⁺) in a dose of 10 ¹³ cm ^{- 2} implanted, with an energy of 100 KeV and using the remaining nitride layer ( 102 ) as a mask.

In Fig. 4B, the formation of an oxide layer ( 106 ) by thermal growth with a thickness of about 400 nm is shown, the remaining nitride layer ( 102 ) was used as a mask, which is then removed. Thereafter, boron ions are implanted in a dose of 3 × 10 ¹² cm ^-2 with an energy of 30 KeV using the oxide layer ( 101 ) as a mask, so as to later describe p-wells ( 108 ) to be described later in FIG. 4C produce.

After the phosphorus ions (P⁺) and the boron ions (B⁺) have been implanted, the semiconductor substrate ( 100 ) is exposed to a temperature of approximately 1150 ° C. for about 12 hours, after which the implanted ions thermally diffuse and diffuse into the Fig. 4C shown n-wells ( 104 a, 104 b, 105 ) and p-wells ( 108 ) are formed with a depth of about 4 microns. The oxide layers ( 101 and 106 ) on the semiconductor substrate who then removed and an SiO ₂ layer ( 110 ) with a thickness of about 20 nm applied by thermal oxidation.

In Fig. 4D, the deposition of a Si ₃ N ₄ nitride layer (112) having a thickness of about 150 nm on the SiO ₂ layer (110) shown by means of CVD, after which the nitride layer by a photoetching process except for active regions (T 1 , T 2 and T 3 ) is removed to form the transistors.

As shown in FIG. 4E, the n-well region ( 105 ) is covered by a photoresist ( 116 ) around the active region (T 3 ) and boron ions (B⁺) with a dose of 1 × 10 ¹³ cm ^-2 and an energy of approximately 30 KeV is implanted to produce a p-type channel blocking layer ( 114 ) to be described later in connection with FIG. 4G.

. 4F is the process state of Fig of the photoresist (116) ent removed and the area outside the n-well region (105) covered by a photoresist (120), after which phosphorus ions (P⁺) in the region around the active area (T 3) in a dose of 10 ¹³ cm ^-2 and implanted with an energy of about 100 KeV to form a barrier layer ( 118 ) described later in FIG. 4G.

After removing the photoresist ( 120 ), as shown in FIG. 4G, a field oxide layer ( 122 ) with a thickness of approximately 500 is formed by thermal growth in an oxide atmosphere at approximately 1000 ° C. using the remaining nitride layer ( 112 ) as a mask nm formed. The remaining nitride layer ( 112 ) is then removed by a wet etching process.

After the nitride layer ( 112 ) is removed, the SiO ₂ layer ( 110 ) is also removed in the process of FIG. 4H and a gate insulation layer ( 124 ) for each transistor in a thickness of approximately 20 nm in an oxide atmosphere at 900 ° C. thermally grown and then polycrystalline silicon deposited and structured by a photo-etching process to form a Ga teelektrodeensicht ( 126 ). In order to reduce the resistance of the gate electrode layer ( 126 ), the polycrystalline silicon is first n-doped after its deposition by diffusion of POCl ₃ at a temperature of approx. 900 ° C and a heat-resistant or a metal layer having a high melting point and a metal silicide layer are applied, after which the process step for gate structuring can be carried out. Tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or cobalt (Co) can be used as heat-resistant metals.

After the gate electrode layer ( 126 ) has been formed, as shown in FIG. 4I, the n-well region ( 105 ) is covered by a photoresist ( 128 ), after which arsenic ions (As⁺) in a dose of 5 × 10 ¹⁵ cm ^-2 and can be planted with an energy of 50 KeV in order to form the drain and source layers ( 130 ) of n-channel transistors in the active regions (T 1 and T 2 ).

After the photoresist ( 128 ) has been removed again, the area outside the n-well area ( 105 ) is covered by a photo resist ( 132 ), as can be seen in FIG. 4J, after which BF ₂ ⁺ ions in a dose of 5 × 10 ¹⁵ cm ^-2 are implanted with an energy of 50 KeV in order to form the drain and source layer ( 134 ) of a p-channel transistor in the active region (T 3 ).

After performing the previous ion implantation steps for the drain and source layers, the photoresist ( 132 ) is removed as shown in FIG. 4K, and a BPSG (boron-phosphorus-silicate glass) layer ( 136 ) is deposited, contact holes ( 138 ) are produced and thereupon a low-resistance wiring layer ( 140 ) is applied and structured by a photoetching method, as a result of which the production of the semiconductor component is completed.

Aluminum (Al) containing 1% Si and 0.5% Cu can be used as the low-resistance wiring layer ( 140 ), if the circuit wiring is carried out by depositing doped polycrystalline silicon and a metallic wiring layer applied thereon. In particular in order to overcome difficulties, such as short circuits caused by Si deposition in the contact area, when increasing the packing density, the hard-melting metal layer, consisting of titanium (Ti), titanium nitride (TiN), tungsten (W), molybdenum (Mo ), Tantalum (Ta) or cobalt (Co), with an increased packing density in the contact area forming a multilayer structure between the aluminum layer and the silicon substrate. The intermediate, hard-melting metal layer in the contact area increases the ESD tolerance in this way.

In the event that the deep transition area according to the invention concurrently with the trough during the CMOS manufacturing process rens is formed, as described above, the doping Atoms of the deep transition region in contrast to the ions implantation through the contact opening in the early stages of Manufacturing process diffused, so the difficulties when the doping atoms are diffused into the deep transition region can be richly eliminated in this process, making the Component according to the invention high reliability in a lot can be made more effectively and easily.

The component described above with a deep n transition region in the p-substrate is to be regarded as exemplary, alternatively For this purpose, a component with egg can be created using the same procedure a deep p-transition region in an n-substrate will.

In addition, although deep n-well transition regions ( 26 a, 26 b) are introduced into both the source region ( 22 a) and the drain region ( 22 b) of the transistor in FIG. 3, it can also be provided that such a deep transition region is formed only in the source region or only in the drain region, in the event that an ESD-tolerant transition is only required for one of these two transistor regions.

Claims (16)

1. Semiconductor device with high reliability

• - a semiconductor substrate ( 20 ; 100 ) of a first conductivity type,
• - Flat transition regions ( 22 a, 22 b; 130 ) of a second conductivity type, which are formed on the top of the substrate ( 20 ; 100 ) with a predetermined depth,
• - Low-resistance wiring layers ( 24 a, 24 b; 140 ), which are formed with the interposition of an insulation layer ( 28 ; 136 ) on the semiconductor substrate ( 20 ; 100 ) and the flat upper transition areas ( 22 a, 22 b; 130 ) through contact holes ( 25 a, 25 b; 138 ) in the insulation layer ( 28 ; 136 ) for connection to an output connection (OT), characterized by
• - At least one deep transition region ( 26 a, 26 b; 104 a, 104 b) of the second conductivity type, which is formed in the semiconductor substrate ( 20 ; 100 ) and contains a contact region within the flat transition region ( 22 a, 22 b; 130 ) and has a sufficient depth to enclose a transition breakthrough region ( 29 ) which arises in the contact region of the low-resistance wiring layer ( 24 a, 24 b; 140 ) with the flat transition region ( 22 a, 22 b; 130 ) due to the from the output connection (OT) supplied static electricity into the substrate ( 20 ; 100 ) extends into it.

2. Semiconductor component according to claim 1, characterized in that the flat transition regions ( 22 a, 22 b; 130 ) form the source and drain layer of a MOS transistor. 3. A semiconductor device according to claim 1 or 2, characterized in that the low-resistance wiring layer ( 24 a, 24 b; 140 ) consists essentially of aluminum and contains silicon. 4. A semiconductor device according to claim 3, characterized in that the low-resistance wiring layer ( 24 a, 24 b; 140 ) also contains additives of copper. 5. Semiconductor component according to claim 1 or 2, characterized in that the low-resistance wiring layer ( 24 a, 24 b; 140 ) consists of highly doped polycrystalline silicon. 6. A semiconductor device according to claim 1 or 2, characterized in that the low-resistance wiring layer ( 24 a, 24 b; 140 ) consists of a multi-layer structure with highly doped polycrystalline silicon and a low-melting metal silicide. 7. Semiconductor component according to one of claims 1, 2 or 6, characterized in that the low-resistance wiring layer ( 24 a, 24 b; 140 ) contains a hard-melting metal layer or a hard-melting metal silicide layer. 8. A semiconductor device according to claim 6 or 7, characterized characterized in that the heavy melting metal tungsten (W), Is titanium (Ti), tantalum (Ta), molybdenum (Mo) or cobalt (Co). 9. Semiconductor component according to one of claims 1 to 8, characterized in that the deep transition regions ( 104 a, 104 b) are generated simultaneously with the formation of trough regions ( 105 , 108 ) of a CMOS semiconductor component. 10. Semiconductor component according to one of claims 1 to 9, characterized in that the semiconductor substrate ( 20 ; 100 ) of the p-type and the deep transition regions ( 26 a, 26 b; 104 a, 104 b) are of the n-type. 11. Semiconductor component according to one of claims 1 to 9, characterized in that the semiconductor substrate ( 20 ; 100 ) of the n-type and the deep transition regions ( 26 a, 26 b; 104 a, 104 b) are of the p-type. 12. Semiconductor component according to one of claims 1 to 11, characterized by

• a first MOS transistor (T 3 ) with a channel of the first conductivity type in a well ( 105 ) of the second conductivity type formed in the semiconductor substrate ( 100 ) of the first conductivity type,
• - A second MOS transistor (T 1 ) with a strat in the semiconductor substrate ( 100 ) formed channel of the second conductivity type and
• - A third MOS transistor (T 2 ) between the first MOS transistor and the second MOS transistor with a channel of the second conductivity type formed in the semiconductor substrate ( 100 ), wherein the second MOS transistor (T 1 ) one in the semiconductor substrate ( 100 ) formed deep transition region ( 104 a, 104 b) of the second conductivity type, which contains a contact region in a source and / or a drain region of the second MOS transistor and has a sufficient depth to that in the contact region of To completely enclose the source or drain region and the transition break-through area that extends into the semiconductor substrate due to static electricity.

13. A semiconductor device according to claim 12, characterized in that the deep transition region ( 104 a, 104 b) of the two th conductivity type of the second MOS transistor (T 1 ) simultaneously with the formation of the trough ( 105 ) of the second conductivity type generated becomes. 14. A semiconductor device according to claim 12 or 13, characterized characterized in that the first conductivity type is the p-type and the second conductivity type is the n type.   15. A semiconductor device according to claim 12 or 13, characterized characterized in that the first conductivity type is the n-type and the second conductivity type is the p-type. 16. Semiconductor component according to one of claims 12 to 15, characterized in that the second transistor (T 1 ) is an output-side transistor in the output stage of the semiconductor component.