DE10116800A1 - Semiconductor device and fabrication method has three-trough structure with imperfections having their distribution of concentration determined in downward direction according to required function - Google Patents

Abstract

A semiconductor device has a three-trough structure. The three troughs (31,35,43) and the other troughs (34,42) contain imperfections. The distribution of concentration for these imperfections is determined in a downward direction according to a required function. This means that required functions like the suppression of a leakage current can be achieved even in a miniaturized structure.

Description

The invention relates to the field of MOS semiconductor devices lines (metal oxide silicon semiconductor devices) and the Process for their preparation and in particular a semi-lead device with tubs of different depths as well as a Process for their production.

According to advances in design and process technology gie it is now possible to build an integrated circuit with high Produce density with multiple integrated circuits is provided, which are the same circuit gene acts as in the prior art on a single chip are manufactured independently. It will now possible to manufacture a structure in which a semiconductor device such as a DRAM (dynamic random access memory) cher) and an integrated logic circuit with high density such as an MPU (microprocessor unit) on a single one Chip are formed. To manufacture such integrated Circuits must have multiple MOS field effect elements with ver  different structures according to the respective purposes in one single chip can be arranged.

A semiconductor device in which memory cells and a Peripheral circuit trained on a common substrate are, for example, in JP 4-212 453 and in JP 5-267 606. These publications have half conductor devices disclosed in which a with storage cell p-well region provided by a transistor transistor from an n region is surrounded.

Fig. 50 is a cross section showing elements of a prior art semiconductor device. In Fig. 50, 101 denotes a p-type semiconductor substrate, 102 an insulation insulating film, 103 an n-type well, and 104 a p-type well. According to this structure, in which the p-well 104 of a memory cell is partially surrounded by the n-well 103 and is thereby electrically insulated from the peripheral circuit part, the potential on the p-well 104 can be determined independently, the n-wells 103 , which surround the p-well 104 intercept electrons coming from the p-semiconductor substrate 101 , so that a soft error can be avoided.

To create a deeper tub, however, must be at the end of the tub a wider area can be provided without a transistor. According to further miniaturization of integrated semiconductors circuit are thus the insulation width and a width the tub as well as the depth of the tub decreased. Consequently the impurity concentration of the tub increases as well Impurity concentration on the surface of the semiconductor sub strats, causing a problem of deterioration in the ele such as an increase in the transition leak current leads. To suppress the transition leakage current the impurity concentration of the tub can be reduced. However, this leads to a problem of a rising tub wi  of course. In particular, the transition leakage current deteriorates the refresh characteristic in the memory cell area.

The invention is therefore based on the object, a half lead device to create an integrated semi-conductor terschaltung can be miniaturized and a memory cell area with improved refreshing characteristics as well as logic circuit with flat tubs are created, the Semiconductor circuit ent miniaturized circuits ent holds who can achieve the required performance, with what they themselves achieve the intended services can and does not have the disadvantages mentioned above, and au also a method for producing such a semi-lead To create device.

This object is achieved by a half lead device according to claim 1 or 13 or by a method ren for manufacturing a semiconductor device according to claim 17. Further developments of the invention are in the dependent An sayings.

According to a feature of the invention, a semiconductor is created direction in which the refreshing data in one Memory cell area are improved, being in a logic circuit area for miniaturization of a circuit structure tur relatively flat tubs are used, whereby the services required in the respective areas in the miniaturized semiconductor integrated circuit with the Memory cell area and the logic circuit area reached can also be a manufacturing process of the semiconductor device is created.

To achieve the above object, a semiconductor contains device according to an aspect of the invention a semiconductor layer of a first conduction type; a first defect  area of a second type of line, which is on a main upper surface of the semiconductor layer is formed and a first Impurity concentration peak; a second sturgeon location area of the first line type that is on the main surface of the semiconductor layer is formed, wherein it in a flat Ge provided with the first impurity region offers and a second impurity concentration peak in a smaller depth than the first impurity concentration has top; a third impurity area from that second type of conduction, which is on the main surface of the semi-lead Is formed layer, wherein it in the in the first Impairment area provided flat area that surrounds second impurity area, and a third impurity area concentration peak at a shallower depth than the first Impurity concentration peak; a fourth sturgeon location area of the second line type, which is on the main surface of the semiconductor layer is formed, wherein it in an area spaced from the first impurity area lies and a fourth impurity concentration peak sits; a fifth impurity area from the first line type that is emitted on the main surface of the semiconductor layer forms, being in one with the fourth impurity cone offers flat area and a fifth disturbance steering concentration peak at a smaller depth than that second and fourth impurity concentration peaks sits; a sixth impurity area from the second lei device type, which is on the main surface of the semiconductor substrate is formed, in one with the fourth Störstel level area, the fifth sturgeon surrounding area and a sixth impurity concentration tip at a smaller depth than the fourth sturgeon steering concentration peak; a first field effect element of the second type of conduction, which is on the main surface of the second impurity region is formed; and a second Field effect element of the second conduction type, which on the  Main surface of the fifth impurity area formed is.

Due to the above structure, a three-tub structure be used to adjust the substrate potential as the element regardless of the semiconductor substrate light and at the same time through the second impurity area suppressed a transition leakage current and through the fifth Impurity area enables miniaturization.

In the semiconductor device of the above aspect, can the first impurity concentration peak and the fourth Impurity concentration peak essentially in the same Chen depth from the main surface of the semiconductor layer be educated. Thus, the first and the fourth sturgeon essentially the same impurity concentration distribution distributions in the direction of the substrate depth, which makes it suitable for the multi-function configuration Semiconductor device with the triple well structure with simple steps can be created.

In this case, the first and third impurity narrow offers in one of the main surface of the semiconductor layer certain depth direction by a certain distance from be spaced apart during the fourth and sixth Impurity area in the from the main surface of the semi lead terschicht determined depth direction by a predetermined Can be spaced from each other. According to the above structure mentioned can be that for the multifunctional configuration tion suitable semiconductor device with the triple well structure be produced without the number of steps is increased.

According to an embodiment of the above aspect the semiconductor device further includes a seventh impurity level  offers of the second conduction type, which is on the main surface the semiconductor layer is formed, wherein it in an in the flat area provided for the first impurity area lies, surrounds the second impurity area and a seventh Impurity concentration peak that is flatter than that first impurity concentration peak and lower than that third impurity concentration peak is and a low less concentration than the first and third impurities has peak concentration; and an eighth impurity constriction offers of the second conduction type, which is on the main surface the semiconductor layer is formed, it being in one with the fourth impurity area is located fifth fault area surrounds and an eighth fault area concentration peak that is flatter than the fourth Impurity concentration peak and lower than the sixth Impurity concentration peak is and a lower one Concentration than the fourth and the sixth impurity con has centering tip.

According to this structure, the first and fourth interferences same area in the direction of the substrate depth job distributions can be the second or fifth Reliable impurity area compared to the semiconductor substrate be electrically insulated. Thus, the semiconductor device direction with the triple well structure obtained for the multi-function configuration is suitable.

According to yet another embodiment of the above In the third aspect, the semiconductor device further includes it Required fault area from the second line type, the the main surface of the semiconductor layer is formed, it being in a region provided with the first impurity region flat area, the second fault area with one surrounds predetermined distance between them, and a seventh Impurity concentration peak that is flatter than that  first impurity concentration peak and lower than that third impurity concentration peak; and a third Field effect element of the first conduction type used in the third impurity area is formed.

According to this structure, the impurity area surrounds with the opposite conductivity type to the substrate second and fifth impurity areas to make them opposite the Electrically isolate the substrate, further comprising the seventh and the second impurity region on the spaced apart Layers are formed. So the third element can even be formed at the end of the third fault area.

The fourth impurity concentration peak can be flatter than be the first impurity concentration peak. According to this The depths of the second and fifth sturgeon structure used the depths of the impurity narrow offer with the lei opposite to the substrate type that reverses the second or fifth fault area ben to change. Thus, a further miniaturization be enough.

According to yet another embodiment, the A semiconductor device of the above aspect ninth impurity area from the first line type that the main surface of the semiconductor layer is formed, being in one of the first and fourth impurity narrows offers different area and a ninth fault location concentration peak at substantially the same depth how the second impurity concentration peak has; on tenth impurity area from the first conduction type that the main surface of the semiconductor layer is formed, being in one of the first, fourth and ninth sturgeons location area is different area and a tenth Impurity concentration peak essentially in the same  depth like the fifth impurity concentration peak owns; an eleventh impurity area from the second lei type, which is on the main surface of the semiconductor layer is formed, in one of the first, fourth, ninth and tenth impurity area different area lies and an eleventh impurity concentration peak in the we noticeably at the same depth as the fifth defect has peak concentration; a twelfth fault area of the second conduction type, which is on the main surface of the Semiconductor layer is formed, wherein it is in one of the first, fourth, ninth, tenth and eleventh impoundment offers different area and a twelfth fault location concentration peak at substantially the same depth how the second impurity concentration peak has; on third field effect element of the second conduction type that the main surface of the ninth impurity area det is; a fourth field effect element from the second lei type, which is on the main surface of the tenth defects area is formed; a fifth field effect element from the first type of conduit, which is on the main surface of the eleventh Fault area is formed; and a sixth field officer fektelement of the first conduction type, which on the main upper area of the fault area is formed.

According to the above structure, the Concentration distribution of the tub, which has no fixed potential needs to be changed, similar to the other tubs. This allows elements to be used that correspond to the required functions be formed.

According to yet another embodiment, the A semiconductor device of the above aspect ninth impurity area from the first line type that the main surface of the semiconductor layer is formed, being in one of the first and fourth impurity narrows  offers different area and a ninth fault location concentration peak at substantially the same depth how the second impurity concentration peak has; on tenth impurity area from the first conduction type that the main surface of the semiconductor layer is formed, being in one of the first, fourth and ninth sturgeons location area is different area and a tenth Impurity concentration peak essentially in the same depth like the fifth impurity concentration peak owns; an eleventh impurity area from the second lei type, which is on the main surface of the semiconductor layer is formed, in one of the first, fourth, ninth and tenth impurity area different area lies and has an eleventh impurity concentration peak; a third field effect element of the second conduction type, that on the main surface of the ninth impurity area is trained; a fourth field effect element of the two th conduction type, which is on the main surface of the tenth sturgeon job area is trained; and a fifth field effect element of the first line type that is on the main surface surface of the eleventh fault area is formed, the third, sixth and eleventh impurity concentration peak in essentially at the same depth as the fifth sturgeon steering concentration peak.

Since according to the above structure, the third, the sixth and the eleventh impurity concentration peak essentially the third, the sixth can lie at the same depth and the eleventh fault area are trained at the same time the.

In the semiconductor device of the above aspect, can the third and sixth impurity concentration peaks flatter than the second impurity concentration peak and be lower than the fifth impurity concentration peak.  

In this case, the concentration distributions in the Controlled that the semiconductor device with an mi niaturized structure and several functions by simple steps can be obtained.

In one embodiment, the semiconductor device includes a second conduction type impurity region, the is formed on the main surface of the semiconductor layer, being in one of the first and fourth areas different area and a concentration of impurities tip at substantially the same depth as that third and sixth impurity concentration peaks sits; and an element of the first conduction type, which in this fault area is formed.

According to this structure, the impurity areas of the counter over the substrate of opposite conductivity type in the Ge offers the three-tub structure and in that of the three-tub structure different areas the same concentration ver divisions that are controlled in such a way that they are equal can be trained in time.

According to a further embodiment, the semiconductor contains device of the above aspect also a defect area of the first conduction type that is on the main surface the semiconductor layer is formed, it being in a Ge offers between the second impurity area and the third Impurity area is and an impurity concentration has a peak that is flatter than the second defect group tration tip is; and an element from the second line type that is formed in this fault area. Since the Impurity areas that have the same potential len are made as flat as possible according to this structure further miniaturization can be achieved become.  

According to a further embodiment, the semiconductor contains device of the above aspect further one on one another main surface of the semiconductor layer lying white tter semiconductor layer with a higher impurity concentration tration than the semiconductor layer. Because according to this structure the elements with multiple functions on the substrate with high concentration, a latching in the deep Section of the tub structure can be suppressed.

A semiconductor device according to another aspect of the Invention includes a semiconductor layer from a first Line type; a first impurity area from a second Conductivity type, which is on a main surface of the semiconductor layer is formed and a first impurity concentration top management; a second impurity area from that first line type, which is on the main surface of the with the first impurity region provided semiconductor layer forms, being full of the first impurity region is constantly surrounded and a second impurity concentration tip at a shallower depth than the first defect has peak concentration; a third fault area of the first conduction type, which is on the main surface of the Semiconductor layer is formed, being in an area lies between the first and the second impurity area, surrounds the second impurity area, and a third sturgeon place concentration peak at a depth less than that has second impurity concentration peak; and a he first field effect element of the second conduction type, the the main surface of the second impurity area det.

Due to the above structure, the third disturbance electric field between the first and the reduce the second impurity area.  

In the semiconductor device of the above aspect needs the impurity area of the second conduction type between the second and third impurity areas to be present. As a result of this structure, the third Impurity area the electric field between the first and suppress the second impurity area.

In one embodiment, the semiconductor device includes a fourth impurity set of the above aspect offers from the first type of conduit that is on the main surface the semiconductor layer is formed, it being in one of the first fault area is different and a fourth impurity concentration peak essentially at the same depth as the second impurity concentration has top; a fifth impurity area from which he Most conduction type, which is on the main surface of the semiconductor layer is formed, it being in one of the first and fourth impurity area is different area and one fifth impurity concentration peak with a smaller one Depth than the second and fourth impurity concentrations has top; a sixth impurity area from that second type of conduction, which is on the main surface of the semi-lead is formed, wherein it is in one of the first, fourth and fifth impurity area different area lies and a sixth impurity concentration peak in the essentially at the same depth as the fifth sturgeon steering concentration peak; a seventh impurity cone offers of the second conduction type, which is on the main surface the semiconductor layer is formed, it being in one of the first, fourth and sixth impurity area which area lies and a seventh impurity concentration tip at substantially the same depth as that fourth impurity concentration peak; a second Field effect element of the second conduction type, which on the  Main surface of the fourth impurity area formed is; a third field effect element from the second lead type that is on the main surface of the fifth impurity is trained; a fourth field effect element of that first line type, which is on the main surface of the sixth Fault area is formed; a fifth field effect element of the first line type that is on the main surface surface of the seventh impurity region is formed; and a capacitor connected to one of the source / drain regions of the first element is connected.

According to the above structure, since a memory cell transi stor is formed in the second impurity area the transition leakage current can be suppressed.

In one embodiment, the semiconductor device includes of the above aspect further a further semiconductor layer that is on another major surface of the half lead layer and a higher impurity concentration than has the semiconductor layer. Because according to this structure the Elements with multiple functions on the substrate with high Concentration can be a latching in deep Section of the tub structure can be suppressed.

A method of manufacturing a semiconductor device according to the invention includes the following steps: training a first impurity region of a second conduction type with a first impurity concentration peak at one Main surface of a semiconductor layer from a first Lei tung type; Forming a second impurity region from the second type of conduction, which is on the main surface of the semi-lead Layer is arranged, it being in one of the first Impurity area is different area and a second Impurity concentration peak; Form one third impurity area from the first conduction type that  the main surface ver with the first impurity area see semiconductor layer is arranged and a third Impurity concentration peak at a depth less than has the first impurity concentration peak; Form a fourth fault area of the first conduction type, that on the main surface of the second impurity cone is provided semiconductor layer and a fourth impurity concentration peak in a smaller one Has depth than the second impurity concentration peak; Forming a fifth impurity region from the second Line type that is on the main surface of the one with the first Interfacial area provided semiconductor layer and a fifth impurity concentration peak in one depth less than the first and third impurities cone centering peak, and forming a sixth sturgeon area of the second line type, which is on the main surface of those provided with the second impurity region Semiconductor layer is arranged, it being the fourth sturgeon surrounds the area and the fifth concentration of impurities has top; Forming a first element of the second conduction type on the main surface of the third sturgeon job area; and forming a second element of the second conduction type on the main surface of the fourth sturgeon job area.

As a result of the above steps, a three-tub structure be used to adjust the substrate potential than the element regardless of the semiconductor substrate Lichen, in which case the second impurity area deep and the fifth impurity area can be flat. Further become the depths of the third and fourth impurities offers used the depths of the impurity areas with the opposite conductivity type to the substrate, the surround the third or fourth fault area.  

According to one embodiment, the method for producing position of a semiconductor device of the invention further the following steps: formation of a seventh impurity level offers the second type of conduit, which is on the main surface the semiconductor layer is arranged, wherein it is in a the flat area provided with the first impurity area, surrounds the third fault area and a seventh sturgeon has peak concentration that is flatter than that highest impurity concentration peak and lower than the fourth Impurity concentration peak and its concentration lower than that of the first and sixth impurity cones center point is; and forming an eighth fault of the second line type, which is on the main upper Surface of the semiconductor layer is arranged, it being in egg nem area provided with the second impurity area lies, surrounds the fourth fault area and the seventh Impurity concentration peak.

Since according to the above steps, the first and fourth Impurity area the same in the direction of substrate depth Impurity concentration distributions can be the second or the fifth fault area by simple steps reliably electrically iso with respect to the semiconductor substrate be lated. Thus, the for the multi-function configuration tion suitable semiconductor device with the triple well structure be preserved.

According to a further embodiment of the method for manufacturing position of a semiconductor device of the invention comprises Step of forming the third impurity region Step of forming a ninth impurity area from the first type of conduit, which is on the main surface of the half conductor layer is arranged in one of the first and of the second fault area is different and has a ninth impurity concentration peak; includes  the step of forming the fourth impurity region Step of forming a tenth impurity area of the first type of conduit, which is on the main surface of the half conductor layer is formed, in one of the first, two ninth and ninth impurity area is different area and has a tenth impurity concentration peak; and includes the step of forming the fifth and sixth Impurity area the step of training an eleventh Impurity region of the second conduction type, which on the Main surface of the semiconductor layer is formed in one of the first, second, ninth and tenth defects len area different area and an eleventh Störstel steering concentration peak.

According to the above steps, the concentration ver division of the tub that has no fixed potential to carry if necessary, similar to that of the other Wan be changed.

In the manufacturing process described above, the fifth, sixth and eleventh impurity concentration peak flatter than the third impurity concentration peak and are lower than the fourth impurity concentration peak.

The invention described above can characterize the following Achieve technical characteristics.

According to the invention, the three well structure is used to the substrate potential of the element regardless of the semiconductor adjust substrate. In this case, the tub that comes with the element is provided by a transition leakage current Damage can be trained to a great depth to achieve the function of the element while the tub, which is provided with the element that is at a transition leak no damage to electricity, for miniaturization in one  small depth is formed. This allows the multiple Functions and miniaturization of the structure at the same time can be achieved. Regardless of the depths of the Ele Tented tubs have the fault areas electrical insulation of the pan provided with the elements the same impurities compared to the semiconductor substrates steering concentrations towards the depth of the substrate. Consequently can the semiconductor device with the multiple functions and with the miniaturized structure by simple steps be preserved.

The impurity area from that opposite the substrate opposite tubing type surrounds the tub to face it electrically isolate the substrate, the impurities concentration distribution of this impurity area from the opposite conductivity type to the substrate changed is to the tub with the flat impurity concentration creating top. Thus, the item can even end Trough be designed so that further miniaturization is achieved.

In the semiconductor device with the three well structure the impurity region of the opposite conduction type, the surrounds the shallow tub, formed at a shallow depth, while the impurity area from the opposite line type that surrounds the deep tub, at a great depth forms is. Thus, the semiconductor device with the meh function and the further miniaturized structure will hold.

The tub that does not need to carry a fixed potential is if necessary configured to be a variable Has concentration distribution. Thus both several functions as well as the miniaturized structure in of the semiconductor device can be obtained at the same time.  

A section of the impurity area, in the Dreiwannen structure the tub of the same conductivity type as the substrate surrounds, has the same concentration distribution as that Impurity area that is formed in another section and is provided with the element. Thus, this sturgeon job areas are trained at the same time, the Semiconductor device with the multi-function structure and with get the miniaturized structure by simple steps can be.

Those in the area of the triple well structure and in the other Area trained fault areas with the opposite of the The opposite conductivity type substrate have the same controlled impurity concentration distributions. So can the semiconductor device with the multi-function structure and with the miniaturized structure by simple steps be created.

In the semiconductor device having the three well structure in the section defined by the impurity area with the ge opposite conductivity type compared to the substrate is, tubs formed with different depths, wherein these tubs even in the event that to these tubs same potential should be applied, as flat as possible are trained. Hence, further miniaturization can be achieved.

In the semiconductor device with the three well structure the memory transistor in the deep well from the same lei tion type as the substrate. Thus the over suppressed current leakage, causing the semiconductor device may have improved refresh characteristics.

In the semiconductor device with the three-well structure  the fault area with the same line type as that Substrate and the flat impurity concentration peak between the tub of the same conductivity type as the substrate and the impurity region of the opposite conduction type, the surrounds this tub. Thus the electric field can be between the tub and the fault area from the opposite Line type and thus the transition leakage current suppressed who that can.

In the semiconductor device with the three well structure the memory cell transistor in the deep well of the same Conductivity type as the substrate formed. Thus, the Semiconductor device are created in which the over current leakage current is suppressed and the refresh characteristics be improved.

Since the elements with multiple functions on the substrate with high concentration, latching in a tie fen section of the tub structure are suppressed, wherein the semiconductor device with improved reliability speed can be achieved.

The three well structure is used to the substrate po potential of the element independent of the semiconductor substrate put. In this case the tub is the one with the element is provided that he damage to a transitional leakage current can suffer, trained in great depth to meet the che function of the element to achieve while the tub, which is provided with the element that is at a transition leak Electricity suffered no damage, trained in the flat tub is to achieve miniaturization. Also have the fault areas for the electrical insulation of each leagues with the elements facing the half conductor substrate regardless of the depths of the tubs in Rich the same depth of impurity concentration  distribution. Thus, the semiconductor device in which the multifunctional structure and the miniaturized structure can be achieved at the same time, by simple steps be.

Also surrounds the impurity area from that opposite the Substrate opposite conduction type the tub to the sub to electrically isolate strat from the tub, the section of the impurity area provided with the element has the flat impurity concentration peak. Consequently the item can even be at the end of the section above be trained so that he further miniaturization can be enough.

In the semiconductor structure with the three-well structure, this can Impurity area of the opposite conduction type that the flat tub surrounds, be formed at a small depth, while the impurity area from the opposite line type that surrounds the deep tub, at a great depth forms can be. Thus, the semiconductor device can multiple functions and the further miniaturized structure have.

A portion of the impurity area from the second lei type of tubing that is of the same line type as the sub strat surrounds, has the same in the three-tub structure Concentration distributions like the impurity area of that second conduction type that is formed in the other section and is provided with the element. So these can be the same be trained early. Thus, the semiconductor device with the multiple functions and with the miniaturized Structure can be created by simple steps.

In the semiconductor device having the three well structure the tubs with different depths in the section  formed by the impurity area with that opposite the Surrounded by the opposite conductivity type, where these tubs even in the event that they have the same bottom potential should be as flat as possible det. Thus, the semiconductor device can further minia be turized.

In the semiconductor device with the three well structure the memory cell transistor in the deep well of the same Conductivity type as the substrate formed. Thus, the Semiconductor device are created in which the over suppressed current leakage current and the refresh characteristic verbes are.

In the semiconductor device with the three well structure the fault area with the same line type as that Substrate and with the flat impurity concentration peak between the tub of the same conductivity type as the substrate and the fault area of the opposite conduction type, that surrounds this tub, trained. Thus, the electri field between the tub and the fault area from opposite line type are suppressed, the Semiconductor device can be created in which the Transition leakage current is suppressed.

In the semiconductor device with the three well structure the memory cell transistor in the deep well of the same Conductivity type as the substrate formed. Thus, the Semiconductor device are created in which the over suppressed current leakage current and the refresh characteristic verbes be tested.

Because the epitaxial growth on the surface of the conc is carried out with high concentration, the Multifunctional elements also trained on in this way  the epitaxial layer is formed. So the latching also in a deep section of the tub structure depressed, the semiconductor device with a verbes reliability can be obtained.

Further features and advantages of the invention result itself from the description of embodiments of the invention based on the figures. From the figures show:

Fig. 1 shows a cross section of a semiconductor device accelerator as a first embodiment of the invention;

Fig. 2 is a plan view of a semiconductor device according to the first embodiment;

Fig. 3-10 are graphs of distributions of impurity concentrations in sections of the semiconductor device along the lines BB, CC, DD, EE, FF, GG, HH and II in Fig. 1 according to the first embodiment;

Fig. 11-13 are cross-sections of the semiconductor device according to the first embodiment;

Fig. 14-20 are cross sections of steps in a process for preparing the Halbleitervorrich processing according to the first embodiment;

FIG. 21 is a cross section of a semiconductor device accelerator as a second embodiment;

FIG. 22 is a plan view of the semiconductor device according to the second embodiment;

Fig. 23-25 are graphs of distributions of impurity concentrations in sections of the Halbleitervor direction along lines KK, LL and MM in Figure 22 according to the second embodiment.

Fig. 26, 27 respectively are cross sections of steps in a process for preparing the Halbleitervorrich processing according to the second embodiment;

FIG. 28 is a cross section of a semiconductor device accelerator as a third embodiment;

Fig. 29-31 are graphs of concentration distributions of the impurity contained in the semiconductor device according to the third embodiment;

FIG. 32 is a cross-section of a step in a procedural ren for manufacturing the semiconductor device accelerator as the third embodiment;

FIG. 33 is a cross section of a semiconductor device accelerator as a fourth embodiment;

Fig. 34, 35 are graphs of distributions of impurity concentrations in sections of the device taken along lines Halbleitervor QQ and RR in Figure 33 according to the fifth embodiment of the invention.

FIG. 36 is a cross section of a semiconductor device accelerator as a fifth embodiment;

Fig. 37, 38 are graphs of distributions of impurity concentrations in sections of the Halbleitervor direction along the lines SS and TT in Figure 36 according to the fifth embodiment.

FIG. 39 is a cross-section of a step in a procedural ren for manufacturing the semiconductor device accelerator as the fifth embodiment;

FIG. 40 is a cross section of a semiconductor device accelerator as a sixth embodiment;

. Fig. 41 is a graph of the distributions of impurity concentrations in a section of the semiconductor device along the line UU in Fig 40 according to the sixth embodiment;

Fig. 42 is a graph of a Störstellenkonzentrationsver distribution of an epitaxial wafer according to the sixth embodiment;

FIG. 43 is a cross section of a semiconductor device accelerator as a seventh embodiment;

FIG. 44 is a plan view of the semiconductor device according to the seventh embodiment;

FIG. 45 is a cross-section of a step in a procedural ren for manufacturing the semiconductor device accelerator as the seventh embodiment;

Fig. 46 is a cross section of a semiconductor device accelerator as an eighth embodiment;

Fig. 47-49 are plan views of the semiconductor device according to the eighth embodiment; and

Fig. 50 the already mentioned cross-section of a semiconductor device of the prior art.

As shown in Fig. 1, a semiconductor substrate contains 1 p or n impurities with a resistivity of about 10 Ω.cm, which corresponds to a concentration of about 1 × 10 ¹⁵ cm ^-3 , while in an isolation region with a Insulation insulating film 2 formed from a silicon oxide film, a silicon nitride film or a silicon oxynitride film is provided. The surface sections of the semiconductor substrate 1 which are insulated by the insulating film 2 are doped with impurities, so that they form the n-wells 31-36 and the p-wells 41-44 .

Fig. 1 shows an example of a semiconductor device with egg ner logic circuit, memory cells and a peripheral circuit. Although not shown, pMOS transistors are formed in the n-wells 33-36 in accordance with the intended applications, while nMOS transistors are formed in the p-wells 41-44 in accordance with the intended applications. However, the n-wells 33 and 35 need not be provided with a transistor, and they each form three-well structures in which the n-well 33 interacts with the n-well 32 (the lower n-well) around the p-well 41 to surround, while the n-well 35 cooperates with the n-well 31 (the lower n-well) to surround the p-well 43 , so that the p-wells NEN 41 and 43 electrically opposite the other sections are isolated.

If necessary, each of the transistors is one Layer such as a penetration barrier layer, the Störstel len of the same conductivity type as the semiconductor substrate (the Tub) contains, or with a doped channel layer, the Impurities (embedded channel type) from opposite to the half conductor substrate (the tub) of the opposite conduction type or Impurities (surface channel type) of the same line type how the semiconductor substrate contains (the tub). These layers are, for example, by ion implantation  NEN formed, but are not shown in the figures.

Fig. 2 is a plan view of the semiconductor device according to the first embodiment of the invention. Fig. 1 shows a cross section along the line AA in Fig. 2. In Fig. 2, the n-well 32 is formed in a portion surrounded by the broken line a in a position which is lower than that of the p-well 41 and the n -Trough 33 is, while the n-well 31 is formed in a section surrounded by the broken line b in a position which is lower than that of the p-well 43 and that of the n-well 35 , so that the p-wells 41 and 43 are electrically insulated from the semiconductor substrate 1 .

Fig. 3 is a graph of the distributions of impurity concentrations in the semiconductor device according to the first embodiment of the invention, and more specifically of the impurity concentrations in the n-wells 32 and 33 and in the semiconductor substrate 1 in a section along the line BB in Fig. 1t . As shown in FIG. 3, contains the n-well 32, the interference filters such as phosphorus with a concentration of about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3, wherein the tip of its impurity concentration in a depth of about 1-1 , 5 microns from the surface of the semiconductor substrate. The n-well 33 contains impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the peak of its impurity concentration being at a depth of about 0.5-0.8 μm from the surface of the semiconductor substrate .

Fig. 4 is a graph of the distributions of impurity concentrations in the semiconductor device according to the first embodiment of the invention, and more specifically of the impurity concentrations in the n-well 32 , in the p-well 41 and in the semiconductor substrate 1 in a section along the line CC in Fig. 1. As shown in Fig. 4, the n-well contains 32 impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the peak of its impurity concentrations at a depth of about 1-1 , 5 microns from the surface of the semiconductor substrate. The p-well 41 contains impurities such as boron with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration lying at a depth of about 0.5-0.8 μm from the surface of the semiconductor substrate . Further, Fig. 4 shows the impurity concentration distribution in a (in Fig. 1, not shown) channel stopper layer, the impurity such as boron at about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 and a Störstellenkon zentrationsspitze at a depth of approximately 0.2 Contains -0.5 µm from the semiconductor substrate surface.

Fig. 5 is a graph of the distributions of impurity concentrations in the semiconductor device according to the first embodiment of the invention, and more particularly of the impurity concentrations in the p-well 42 and in the semiconductor substrate 1 in a section along the line DD in Fig. 1. With Except that the n-well 32 is not formed, the impurity concentration distributions in this section are the same as in FIG. 4.

Fig. 6 is a graph of the distributions of impurity concentrations in the semiconductor device according to the first embodiment of the invention, and more specifically of the impurity concentrations in the n-well 34 and in the semiconductor substrate 1 in a section along the line EE in Fig. 1. How as shown in Fig. 6, the Störstellenkonzentrationsver distributions are in this section, except that the n-well 32 is not formed, the same as in Fig. 3.

Fig. 7 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the first imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-wells 35 and 31 and in the semiconductor substrate 1 in a section of line FF longitudinally in Fig. 1 As shown in Fig. 7, the n-well 31 contains impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the peak of its impurity concentration at a depth of about 2-2.5 µm lies from the surface of the semiconductor substrate. The n-well 35 contains impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the impurity concentration peaks at a depth of about 1-1.5 μm and at a depth of about 0.5- 0.8 µm from the surface of the semiconductor substrate.

Fig. 8 is a graph of the distributions of impurity concentrations in the semiconductor device according to the first embodiment of the invention, and more specifically of the impurity concentrations in the n-well 31 , in the p-well 43 and in the semiconductor substrate 1 in a section along the line GG in Fig. 1. As shown in Fig. 8, the n-well 31 contains impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the peak of its impurity concentration at a depth of about 2- 2.5 microns from the surface of the semiconductor substrate lies. The p-well 43 contains impurities such as boron with approximately 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the peak of its impurity concentration being at a depth of approximately 1-1.5 μm from the surface of the semiconductor substrate. Further, Fig. 8 shows the impurity concentration distribution in a (in Fig. Not shown 1) channel stopper layer, the impurity such as boron at about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 and the impurity concentration peak at a depth of about 0, Contains 2-0.5 µm from the semiconductor substrate surface.

Fig. 9 is a graph of the distribution of impurity concentration in the semiconductor device according to the first embodiment of the invention and more specifically the impurity concentration distribution in the p-well 44 and in the semiconductor substrate 1 in a section along the line HH in Fig. 1. How in Fig. 9, the Störstellenkonzentrationsver distributions are in this section, except that the n-well 31 is not formed, the same as in Fig. 8.

Fig. 10 is a graph of the distributions of impurity concentrations in the semiconductor device according to the first embodiment of the invention, and more specifically of the impurity concentrations in the n-well 36 and in the semiconductor substrate 1 in a section along the line II in Fig. 1. How as shown in Fig. 10, the impurity concentration distributions are in this section with the exception that the n-well 31 is not formed, the same as in Fig. 7.

Although the impurity concentration distributions, for example the impurity concentration can be described and the depth of the location of the impurity concentration peak of course according to the conditions required in the transistors and the design regulations for the tub insulation be changed.

Fig. 11 is a cross section of the semiconductor device according to the first embodiment of the invention which increases the memory cell area in the state shown in Fig. 1 portion of the semiconductor apparatus.

As shown in Fig. 11, a transistor of a DRAM memory cell serving as a first field effect element has a gate length L ₁ of about 200 nm. In this case, the width of the insulation insulating film 2 changes depending on the position, wherein its minimum insulation width 100 nm-200 nm and its width in the other layers is about 200 nm-400 nm. The insulating film 2 has a thickness of about 150-500 nm.

On the surface of the semiconductor substrate 1 provided with the p-well 43 , a gate oxide film 5 having a thickness of about 5-10 nm is formed, while a polycrystalline silicon layer and a gate electrode 6 are formed on the gate oxide film 5 . This polycrystalline silicon layer has a thickness of approximately 150-250 nm and contains n-type impurities such as phosphorus or arsenic with a concentration of approximately 2-15 × 10 ²⁰ cm ^-3 . The gate electrode 6 has a thickness of approximately 40-60 nm and contains a layer of metal (silicide) such as tungsten silicide.

The source / drain regions 81 and 82 contain impurities such as phosphorus or arsenic with approximately 1 × 10 ¹⁵ cm ^-3 . Via a contact hole 16 , which is formed in an interlayer insulating film 121 , which contains, for example, a TEOS oxide film (tetraethyl orthosilicate oxide film), an interconnection 18 is connected to the source / drain region 82 . Furthermore, a capacitor is connected to the source / drain region 81 via a contact hole 17 which is formed in an interlayer insulating film 122 which contains, for example, a TEOS oxide film. The capacitor includes a storage node 13 containing polycrystalline silicon and phosphor of about 1-5 × 10 ²⁰ cm ^-3 , a capacitor insulating film 14 with a thickness of about 5-10 nm which contains a silicon nitride oxide film, and a cell plate 15 which contains polycrystalline silicon with about 1-5 × 10 ²⁰ cm ^-3 phosphorus. The storage node 13 is connected to the source / drain region 81 via the contact hole 17 . Although the capacitor shown in the figure is of the stack type, it may be of another type such as a trench type.

On the surface of the semiconductor substrate 1 provided with the n-well 35 , a gate oxide film 5 is formed with a thickness of about 5-10 nm. A polycrystalline silicon layer and the gate electrode 6 are formed on the gate oxide film 5 . This polycrystalline silicon layer has a thickness of approximately 150-250 nm and contains p-type impurities such as boron with approximately 2-15 × 10 ²⁰ cm ^-3 . The gate electrode 6 has a thickness of approximately 40-60 nm and is formed from a layer of metal (silicide) such as tungsten silicide. The polycrystalline silicon layer may contain n-type impurities, such as phosphorus or arsenic, in which case the channel region is doped with impurities in order to optimize the threshold voltage. The gate electrode 6 does not need to contain the metal layer (silicon layer) and can only be formed from the polycrystalline silicon layer. In some cases, the polycrystalline silicon layer in the nMOS transistor contains n impurities, while the polycrystalline silicon layer in the pMOS transistor contains p impurities, so that a dual gate structure is used.

The source / drain regions 91 and 92 contain impurities such as boron with 1 × 10 ¹⁸ cm ^-3 .

In the figures showing the above structure, only the p-type well 43 is formed in the area surrounded by the n-type wells 35 and 31 . In general, however, the transistors of the memory cells provided with such transistors are designed in a matrix form.

In the figure, only one pMOS transistor is formed in each n-well 35 . However, a plurality of pMOS transistors can be formed in the n-well 35 , or no transistor can be formed in the n-well 35 . If a plurality of pMOS transistors are formed, each transistor is generally insulated from the others by an insulation insulating film, but the plurality of transistors can be formed in a single active region.

Except that the n-well 31 is not formed, the transistors in the peripheral area have essentially the same structures as those in the memory cell area.

Fig. 12 is a cross section of a semiconductor device according to the first embodiment of the invention which increases the memory cell area of the semiconductor device in the cross section of Fig. 1. Fig. In Fig. 12, 811 and 911 denote source / drain regions, respectively. As shown in FIG. 12, a transistor having the source / drain regions 811 and 911 can be formed in the p-well 43 in addition to the transistors of the memory cell for another purpose.

FIG. 13 is a cross section of the semiconductor device according to the first embodiment of the invention, which shows in greater detail in the logic section area of the semiconductor device shown in the cross section of FIG. 1, a portion provided with the p-well 32 .

The gate length L _{2 of} the transistor serving as the second field effect element in the logic circuit area is approximately 200 nm. In this case, the insulation insulating film 2 in the logic circuit area has a width of approximately 200-500 nm and a thickness of approximately 150-500 nm. Local the insulation film 2 can have a width of about 5000 nm. In this case, the width of the insulation insulating film 2, for example, by leaving the semiconductor substrate 1 (a dummy pattern) in a portion not to be used for forming the element, is adjusted so that irregularities (such as recesses and curvatures) on the surfaces of the semiconductor substrate 1 and the insulating film 2 can be suppressed.

The source / drain regions 83 and 84 contain impurities such as phosphor or arsenic with approximately 1 × 10 ²⁰ cm ^-3 and act with the source / drain regions 81 and 82 , the impurities such as phosphor or arsenic with 1 × 10 ¹⁸ cm ^-3 , together to form LDD structures (lightly doped drain structures). The source / drain regions 93 and 94 contain impurities such as boron or boron fluoride with about 1 × 10 ²⁰ cm ³ and act with the source / drain regions 91 and 92 , the impurities such as boron or boron fluoride with 1 × 10 ¹⁸ cm 3 ^-3 included, together to form LDD structures (lightly doped drain structures). The LDD structure is used if necessary, while the source / drain regions 81 , 82 , 91 and 92 are not formed in certain cases.

The thickness of the gate oxide film 5 in the logic circuit area may be similar to that of the gate oxide film in the DRAM memory cell, but is preferably in the range of about 4-7 nm because the smaller thickness provides a faster transistor in which a sufficient ON - Current can flow and the drive capacity is high. The structures of the gate electrode 6 and a sidewall insulating film 7 in the logic circuit are similar to those of the DRAM memory cell.

Although not shown, the structure is also provided with interconnections connected to the source / drain region 91 or 92 through a via hole formed in the interlayer insulating films 121 and 122 .

Although the embodiment is that described by way of example Interconnections are used, the number and the number order of the intermediate formed between the transistors Layer insulation films changed depending on the circuit structure.

As shown in the figure, in the above description, only one p-well 41 is formed in the area surrounded by the n-wells 32 and 33 . In the above area, however, two or more p-wells 41 can be formed, while two or more n-wells 33 can also be formed. Although a transistor is formed in both the n-well 41 and the p-well 33 , two or more transistors can also be formed. No transistor needs to be formed in the p-well 33 . In the multi-transistor structure, each transistor is generally isolated from the others by the insulation insulating film, but the multiple transistors may be formed in a single active region.

The structures of the transistors (not shown) formed in the logic circuit area in the n- and p-wells 34 and 42 are similar to that of the transistor in the area provided with the n-well 32 , the arrangement and the number of p - And n-tubs 42 and 34 , the number of transistors formed in the tub and other, depending on the circuit arrangement.

The arrangement of the logic circuit area, the memory cells area and the peripheral circuit area have been exemplified described and are not based on the above arrangement limited.

The gate electrode 6 can only contain a metal such as copper, can only be formed from polycrystalline silicon with impurities and can optionally have different structures.

If necessary, in the logic circuit area in which Memory cell area and in the peripheral circuit area Impurity areas or the like (not shown) forms to prevent a penetration between the elements other.

The operations will now be described. In the DRAM memory  cher cell are accumulated by means of a capacitor electrical charges information stored, being in refreshing (reading / writing) at constant intervals leads. If over that connected to the capacitor Element a transition leakage current flows, the go in the Kon information stored in capacitor excessively where the refreshing characteristic data (data holding characteristic data) ver worse. So it is compared to the transistors in The other sections also important that the leakage current is suppressed.

To write data into the capacitor, a voltage VG of 3.6 V and a voltage VB of -1.0 V are applied to the respective electrodes of the memory cell, while the interconnection 18 (connected to the source / drain region 82 ( Bit line) a voltage of 0 V and a voltage of 1.0 V is applied to the cell plate 15 . To erase data, a voltage VG of 3.6 V and a voltage VB of -1.0 V is applied, while at the interconnection 18 connected to the source / drain region 82 , a voltage of 2.0 V and to the Cell plate 15 a voltage of about 1.0 V is applied. To read data, the voltage applied to the bit line is set to approximately 1.0 V. These voltage values are only examples and vary depending on the thickness of the gate oxide film and the gate length.

In the logic circuit, the gate electrode 6 , the source / drain regions 81-84 and 91-94 and the semiconductor substrate 1 (to the n-wells 32-34 and to the p-wells 41 and 42 ) Voltages are applied, a channel being formed in the surface of the semiconductor substrate 1 under the gate electrode 6 . As a result, one of the paired regions 81 and 83 ( 91 and 93 ) and one of the paired regions 82 and 84 ( 92 and 94 ) form the sources, while the other forms the drains, so that the structure acts as a circuit. For example, in the case of the nMOS transistor, a VG of approximately 2.5 V, a VD of approximately 2.5 V, a VS of approximately 0 V and a VB of approximately 0 V are applied to the respective electrodes in the logic circuit. In the case of a pMOS transistor, a VG of approximately 0 V, a VD of approximately 0 V, a VS of approximately 2.5 V and a VB of approximately 2.5 V are applied to the respective electrodes in the logic circuit. These voltage values are only examples and vary depending on the thickness of the gate oxide film and gate length.

As described above, those are in the logic circuit area trained transistors to control the circuit operations on the transistors in the memory cell area and connected in the peripheral area.

According to the semiconductor device of the first embodiment the deterioration of element characteristics such as Increase in leakage current across the pn junction between the Semiconductor substrate (the tub) and the source / drain region in a portion in the memory provided with the capacitor cell area are suppressed even if the Depth of the tub according to the reduction in insulation width and the tub depth because of the miniaturization of the integrier th semiconductor circuit is reduced, whereby the refresh characteristics can be improved.

The transistor in the DRAM memory cell area is in the deep p-tub surrounded by the lower n-tub. This enables the potential to be switched on regardless of the substrate and a soft error can be suppressed.

Because the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the, the potential on the three tubs independently can be set so that even with the transistors  logic circuit provided with various functions achieve various required performances and several Can have functions.

The following is a method of making the semi-lead device according to the first embodiment of the invention described.

Figs. 14-20 are cross sections of steps in the method for manufacturing the semiconductor device according to the first embodiment. In Fig. 14, 21 denotes a silicon oxide film, 22 a silicon nitride film and 23 a groove. As shown in Fig. 14, a silicon oxide film 21 having a thickness of about 5-30 nm and a silicon nitride film 22 having a thickness of about 100-300 nm are formed on the surface of the silicon substrate 1, with silicon nitride film 22 and on anisotropic etching is performed on the silicon oxide film 21 lying on the isolation region to selectively remove them using a photoresist mask (not shown). After removal of the photoresist mask, an anisotropic etching is carried out on the semiconductor substrate 1 masked with the silicon nitride film 22 , so that the grooves 23 each have a width of approximately 200-500 nm and a depth of approximately 150- on the surface of the semiconductor substrate 1 500 nm are formed. Fig. 14 shows a sectional structure of the elements of the semiconductor device after completion of the foregoing step.

Then, a low-pressure CVD process is carried out to form an insulating film on the entire surface, which contains, for example, a silicon oxide film with a thickness of about 300-800 nm and is not shown, whereupon a CMP process (chemical mechanical Polierverfah ren) is performed with the silicon nitride film 22 as a barrier to remove the silicon oxide film on the surface of the silicon nitride film 22 , so that the silicon oxide film remains only in the grooves 23 and in the openings of the silicon nitride film 22 . Subsequently, wet etching with hot phosphoric acid is carried out to remove the silicon nitride film 22 , whereupon the silicon oxide film 21 is removed so that the insulation insulating film 2 is formed.

Fig. 15 shows a sectional structure of the elements of the semiconductor device after completing the above step.

As shown in FIG. 16, thermal oxidation is carried out on the surface of the silicon substrate 1 to form a silicon oxide film 24 having a thickness of about 10 nm. A photoresist mask 301 is formed with an opening above the surface of the memory cell area and high energy implantation of the n-type impurities such as phosphorus is performed on the entire surface to be under the conditions of about 2-10 MeV and 1 × 10 ¹² -1 × 10 ¹⁴ cm ^{-2 to form} the n-tub 31 . Fig. 16 shows a sectional structure of the elements of the semiconductor device after completing the above step. The photoresist mask 301 is then removed.

In Fig. 17, a photoresist mask 302 is formed. The photoresist mask 302 has openings over the surfaces of those portions that form the three-well structures of the n-well training area in the memory cell area, the n-well training area in the peripheral area and in the logic circuit area. The high energy implantation of the n-type impurities such as phosphorus is carried out on the entire surface masked with the photoresist mask 302 under the conditions of about 500 kev-3 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^-2 . As a result, the n-wells 35 and 36 are partially formed and the n-well 32 is formed. Fig. 17 shows a sectional structure of the elements of the semiconductor device after completion of the above step. The photoresist mask 302 is then removed.

As shown in Fig. 18, a photoresist mask 303 is formed. The photoresist mask 303 has openings over the surfaces of the p-well training area in the memory cell area and the p-well training area in the peripheral area. A high energy implantation of p-type impurities such as boron is performed on the entire surface masked with the photoresist mask 303 under the conditions of about 300 keV-1.5 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^-2 . As a result, the p-wells 43 and 44 are formed. Fig. 18 shows a sectional structure of the elements of the semiconductor device after completion of the above step. Thereafter, the photoresist mask 303 is removed.

As shown in FIG. 19, a photoresist mask 304 is formed. The photoresist mask 304 has openings over the surfaces of the n-well formation areas both in the memory cell area and in the peripheral area and in the logic circuit area. A high-energy implantation of the n-type defects, such as phosphorus, is carried out on the entire surface masked with the photoresist mask 304 under the conditions of approximately 200 keV-2 MeV and approximately 1 × 10 ¹² -1 × 10 ¹⁴ cm ^-2 . As a result, the n-wells 35 and 36 are partially formed and the n-wells 33 and 34 are ausgebil det. Fig. 19 shows a sectional structure of the elements of the semiconductor device after completion of the above step. Thereafter, the photoresist mask 304 is removed.

As shown in FIG. 20, a photoresist mask 305 is formed. The photoresist mask 305 has openings over the surfaces of the p-well training areas in the logic circuit area. A high energy implantation of p-type impurities such as boron is performed on the entire surface masked with the photoresist mask 305 under the conditions of about 150 keV-1 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^-2 . As a result, the p-wells 41 and 42 are formed. Fig. 20 shows a sectional structure of the elements of the semiconductor device after completion of the above step. Thereafter, the photoresist mask 305 is removed.

If necessary, the photoresist masks are formed wherein the ion implantation to form the through handle barrier layer and the channel implantation layer out leads. Even if these impurity layers for the transistors in different areas under the logic circuit area, the memory cell area and the peripheral can be used in this area conditions, such as the impurity concentration distribution are the same, who is trained at the same time the. The respective tubs can be arranged in any row be trained.

The silicon oxide film 24 is then removed. The silicon oxide film 24 is provided to protect the surface of the silicon substrate 1 against damage from the various types of ion implantations for tub formation etc. and 78078 00070 552 001000280000000200012000285917796700040 0002010116800 00004 77959 against contamination by the photoresist.

Then, by thermal oxidation, a silicon oxide film or the like having a thickness of about 5-10 nm is formed as a gate insulating film 5 on the entire surface of the semiconductor substrate 1 . If the thickness of the gate oxide film 5 in the logic circuit area is to be smaller than in the other areas, after forming the silicon oxide film with a thickness of about 4-7 nm on the entire surface, the silicon oxide film is removed from the logic circuit area by the thermal oxidation and then a silicon oxide film with a thickness of 3-7 nm is formed to provide the gate insulating film 5 .

A polycrystalline silicon layer is formed on the entire surface by an LPCVD process (low-pressure CVD process), which contains n-type impurities such as phosphorus with approximately 1 × 10 ²⁰ -5 × 10 ²⁰ cm ^-3 and a thickness of approximately 150-250 nm, whereupon it is patterned to form the gate electrode 6 . In order to provide the gate electrode with a double layer structure with a polycrystalline silicon layer and a metal layer (silicide layer), after forming a polycrystalline silicon layer with a thickness of approximately 150-250 nm, the n-type impurities such as phosphorus with approximately 2-15 × 10 ²⁰ cm ^-3 contains a metal layer (silicide layer) such as a tungsten silicide layer with a thickness of about 40-60 nm formed, whereupon these layers are structured. The impurities contained in the gate electrode can be p-type impurities such as boron.

The gate electrode of an nMOS transistor can contain n impurities, while the gate electrode of a pMOS transistor can contain p impurities. To prepare this double-gate structure, a polycrystalline silicon layer without impurities is formed on the entire surface after the gate insulating film 5 has been formed, whereupon the n- and p-impurities are implanted in the suitably masked nMOS or pMOS regions by ion implantation become.

A photoresist mask (not shown) is then formed which covers the nMOS region, whereupon implants such as boron are implanted into the entire surface with approximately 40 keV and approximately 1 × 10 ¹⁴ cm ⁻² p defects, such as boron / Drain regions 91 and 92 are formed.

A photoresist mask (not shown) is formed which covers the pMOS region, whereupon it is implanted in the entire surface with about 40 keV and 1 × 10 ¹⁴ cm ^-2 n impurities such as phosphorus or arsenic by ion implantation, so that the source / drain regions 81 and 82 are formed.

In the above method, processing becomes out form the source / drain regions in the pMOS region independently of processing for the nMOS area. This independent processing is not only in the above Executed case in which the difference in terms of Lei type exists, but also in the case where a Difference in concentration, the concentrati distribution or the like is present, the Mas ken can be used to achieve the desired conditions pass. The implantation conditions vary depending on whether or not the drain region has the LDD structure, where for the ion implantation for the nMOS area and for the pMOS area in the reverse order as outlined above can be led.

Then, the CVD process is carried out to form an insulating film such as a silicon oxide film having a thickness of about 30-100 nm on the entire surface, followed by etching back to form the side wall insulating film 7 . To prepare the source / drain regions with the LDD structure, p-impurities such as boron or n-impurities such as phosphorus or arsenic are inserted into the pMOS region or with approximately 100 keV and approximately 1 × 10 ¹⁵ cm ^−2. implanted in the nMOS region so that the source / drain regions 83 , 84 , 93 and 94 are formed.

A sidewall 10 may be a layer film containing a silicon oxide film and a silicon nitride film. In this case, after forming the silicon oxide film with RTO (thermal rapid oxidation), the silicon nitride film is deposited with the CVD method and then etching back is carried out to complete the side wall 10 .

Ion implantation can be performed on the nMOS and pMOS areas in in the opposite order.

If a metal silicide layer is to be formed on the surfaces of the gate electrode 6 and the source / drain regions 81-84 and 91-94 in the logic circuit area, cobalt can be deposited on the structure in the above-mentioned phase, whereupon an RTA Processing (rapid thermal annealing processing) is performed so that a reaction to form a metal silicide layer occurs in the portion where the silicon is exposed. Although not shown, the cobalt that remains without causing a reaction is subsequently removed.

The silicon oxide film forming the interlayer insulating film 121 with a thickness of approximately 200-600 nm is deposited using the low-pressure CVD method and then a contact hole 16 with a diameter of approximately 0.1 μm-0.5 is used using the dry etching method µm is formed, which reaches the source / drain region 82 in the memory cell region. After the via 16 is filled with an interconnect material by the CVD method, the patterning is carried out to trigger the interconnect 18 . Likewise, the interlayer insulating film 122 is formed, the contact hole 17 is formed which reaches the source / drain region 81 in the memory cell region, and a capacitor connected via the contact hole 17 is formed. In a similar manner, interconnections are also formed which are connected to the source / drain regions in regions other than the memory cell region.

The connection structure between the contact holes and the  Interconnections can be just like the order in which these sections are formed according to the circuit diagram order to be changed. In addition, an intermediate connection formation at a higher level of structure with another Interlayer insulating film are formed in between, so that the multilayer interconnections are used can. The interconnect material can be polycrystalline lines silicon, which with impurities or with a me tall is doped. If the metal is used, will be on a barrier metal such as the inside wall of each contact hole TiN is designed to diffuse the material into the Prevent source / drain areas.

In this way, the semiconductor device is formed with the transistors shown in FIG. 11 in the memory cell area and with the transistors shown in FIG. 13 in the logic circuit area.

According to the method of manufacturing the semiconductor device the first embodiment of the invention, the tub in the memory cell area even in the case where the depth the tub according to the reduction in insulation width and the Tub width because of the miniaturization of the integrated Semiconductor device is reduced, with great depth be formed. Accordingly, deterioration can of element characteristics such as an increase in leakage current via the pn junction between the semiconductor substrate (the Tub) and the source / drain region suppressed and the on fresh data are improved.

Because the verse with the transistor in the memory cell area hene p-well in the manufactured in the above method Semiconductor device is surrounded by the lower n-well, can set the potential regardless of the substrate and the soft error can be suppressed.  

Because the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the, the potential on the three tubs independently can be set so that even with the transistors logic circuit provided with various functions achieve various required performances and several Can have functions. The semiconductor device with these Advantages can be achieved by the simple steps the.

The lower n-tub that is on the bottom of the p-tub in the three wells of the logic circuit area is formed trained simultaneously with the n-tub, which in the three Wells of the memory cell area on the side of the p-well is trained. Thus the number of required Masks and the number of masking steps reduced become.

The p- surrounded by the n-wells of the three-well structures Wells in the memory cell area and in the logic scarf area can be trained in different steps different concentration distributions create. Accordingly, the nMOS transistors can different characteristics are formed, the Vor direction with multiple functions can be created.

Second embodiment

Fig. 21 shows a semiconductor device according to a second embodiment of the invention, which is for example provided with a logic circuit, memory cells and a peripheral circuit. Although not shown, pMOS transistors are formed in the n-wells 33 , 34 , 351 and 36 for the respective purposes, while nMOS transistors are formed in the p-wells 41-44 for the respective purposes. In some cases, no transistor is formed in the n-wells 33 and 351 . The n-wells 33 and 331 surround the p-well 41 together with the n-well 321 (lower n-well), while the n-wells 351 and 352 surround the p-well 43 together with the n-well 31 (lower n Tub) surrounded. In this way, the p-wells 41 and 43 are electrically insulated from the other sections, whereby the three-well structure described above is created. The n-well 352 has a width of approximately 0.5-2.0 µm.

Fig. 22 is a plan view of the semiconductor device according to the second embodiment of the invention. FIG. 21 shows a section along the line JJ in FIG. 22. In FIG. 22, the hatched n-well 331 is formed in a lower position than the n-well 33 . A portion surrounded by the dashed line c is provided with the n-well 321 , which lies at a greater depth than the p-well 41 and the n-wells 33 and 331 , so that the p-well 41 is electrically opposite to the semiconductor substrate 1 is isolated. The hatched n-well 353 is formed to a greater depth than the n-well 351 . In the n-well 31 , a portion surrounded by the broken line d is provided, which is lower than the p-well 43 and the n-wells 351 and 352 , so that the p-well 43 is electrically insulated from the semiconductor substrate 1 .

The semiconductor device according to the second embodiment differs from the semiconductor device of the first embodiment in that in the memory cell region in a portion that is between the n-well 351 formed in a flat position and the n-well 31 , the n-well 352 is formed, the impurity concentration of which decreases in the deep direction of the substrate in order to compensate for the impurity concentration, while in the logic circuit region in a section which is formed between the n-well (lower n-well) 321 and the n- Well 33 lies, the n-well 351 is formed, the impurity concentration drops in the depth direction of the substrate in order to compensate for the impurity concentration. Except for the above, the structures are the same as those of the semiconductor device of the first embodiment. The three-well structure in either the logic circuit area or the memory cell area of the second embodiment can be replaced by the three-well structure in the first embodiment.

Fig. 23 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the second imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-wells 33, 331 and 321 as well in the semiconductor substrate 1 in a section along the line KK in Fig. 22. As shown in Fig. 23, the n-well 33 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip of its impurity concentration at a depth of about 0.5 -0.8 microns from the surface of the semiconductor substrate. The n-well 331 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration being at a depth of about 1-1.5 μm from the upper surface of the semiconductor substrate . The n-well 321 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration being at a depth of about 2-2.5 μm from the surface of the semiconductor substrate .

FIG. 24 is a graph of the impurity concentration distributions in the semiconductor device according to the second embodiment of the invention, and more specifically, the impurity concentration distributions in the n-wells 33 and 321 and the semiconductor substrate 1 in a section along the line LL in FIG. 22. As shown in Fig. 24, the n-well 33 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip of its impurity concentration at a depth of about 0.5-0 , 8 microns from the surface of the semiconductor substrate. The n-well 321 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration being at a depth of about 2-2.5 μm from the surface of the semiconductor substrate .

Fig. 25 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the second imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the p-well 41 in the n-well 321 and the semiconductor substrate 1 in a section along the line MM in Fig. 22. As shown in Fig. 25, the p-well 41 contains the impurities such as boron with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip of its impurity concentration at a depth of about 0.5-0.8 microns from the surface of the semiconductor substrate. Further, Fig. 25 shows the impurity concentration distribution in a (in Fig. Not shown 21) channel stop layer len the Störstel such as boron of about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 contains, where at the impurity concentration peak at a depth of about 0.2-0.5 microns from the semiconductor substrate surface.

According to the semiconductor device of the second embodiment the deterioration of element characteristics such as that Increase in leakage current across the pn junction between the Semiconductor substrate (the tub) and the source / drain region in a portion in the memory provided with the capacitor are suppressed even in the case that the depth of the tub in accordance with the reduction the insulation width and the tub depth because of the miniatures  the semiconductor integrated circuit is reduced, which can be used to improve the refresh characteristics.

The transistor in the DRAM memory cell area is in the deep p-tub surrounded by the lower n-tub. This enables the potential to be switched on regardless of the substrate and a soft error can be suppressed.

Because the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the, the potential on the three tubs independently can be set so that even with the transistors logic circuit provided with various functions achieve various required performances and several Can have functions.

In general, a transistor which is formed in a well having a impurity concentration peak at a great depth from the surface of the semiconductor substrate must be spaced a certain distance from the end of the well in order to suppress deterioration of the transistor characteristics. However, in the semiconductor device according to the second embodiment, the n-wells 331 and 352 are spaced from the p-wells 41 and 43 , respectively, so that higher miniaturization can be achieved.

There will now be a method of manufacturing the semiconductor direction according to the second embodiment of the invention wrote.

FIGS. 26 and 27 respectively show cross sections of steps in a method of manufacturing the semiconductor device according to the second embodiment.

First, similar to the first embodiment, the insulation insulating film 2 and the silicon oxide film 24 are formed on the surface of the semiconductor substrate 1 . A photoresist mask 306 is then formed with an opening above the surface of the area in which the triple well structure is formed, whereupon on the entire surface masked with the photoresist mask 306 under the conditions of about 2-10 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^ä2 a high-energy ^{implantation of} the n-impurities such as phosphorus is carried out. As a result, the n-wells 31 and 32 are formed. Fig. 26 shows a sectional structure of the elements of the semiconductor device after completing the above step. The photoresist mask 306 is then removed.

In Fig. 27, 307 denotes a photoresist mask. The photoresist mask 307 has openings over the surface of the area in which the n-wells 31 and 321 are in contact with the semiconductor substrate 1 , ie over the ends of the n-wells 31 and 321 and the n-well training area of the Peripherie offers A high-energy implantation of the n-type impurities such as phosphorus is carried out on the entire surface masked with the photoresist 307 under the conditions of approximately 500 keV-3 MeV and approximately 1 × 10 ¹² -1 × 10 ¹⁴ cm ^-2 . As a result, who formed the n-wells 331 , 352 and 36 . Fig. 27 shows a sectional structure of the elements of the semiconductor device after completion of the above step. Thereafter, the photoresist mask 307 is removed.

The p-wells 41-44 and the n-wells 34 and 351 are formed similarly to the first embodiment. The n-well 351 be the same impurity concentration distribution as the n-wells 33 and 34 and is formed simultaneously with them in the manufacturing process. Thereafter, the required elements are formed in the respective tubs similar to those in the first embodiment.

The n-well 36 can be formed in the step of forming the n-wells 33 , 34 and 351 and thus simultaneously with them. In this case, the n-well 36 has the same concentration distribution as the n-wells 33 , 34 and 351 . If, as described above, the formation in the same step is permissible, it can be achieved that the mask for forming the n-well 36 and the ion implantation step can be omitted using them.

In the method for manufacturing the semiconductor device of the second embodiment, the n-wells 321 , 331 , 351 and 352 are formed in a different manner than in the method for manufacturing the semiconductor device of the first embodiment. Except for the above, the structures are formed in the same manner as in the first embodiment. The order of formation of the respective wells and the interconnection structure can be changed similarly to the first embodiment, and the three-well structure in either the logic circuit area or the memory cell area of the second embodiment can be replaced by the three-well structure in the first embodiment.

In the manner described above, the semiconductor device having the well structure shown in FIG. 21 is formed.

According to the method of manufacturing the semiconductor device the second embodiment, the tub in the memory cell area even in the case of great depth be formed that the depth of the tub according to the verring tion of the insulation width and the tub width because of the Mi Niaturization of the integrated semiconductor substrate is reduced is. Accordingly, deterioration of the item characteristics such as an increase in the leakage current above the pn Transition between the semiconductor substrate (the tub) and the  Source / drain area are suppressed, the refresh characteristics can be improved.

Because the verse with the transistor in the memory cell area hene p-tub is surrounded by the lower n-tub, this can Potential set independently of the substrate and the soft one Error in the manufactured in the above procedure Semiconductor device can be suppressed.

Since the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the, the potential on the three tubs independently can be set so that even with the transistors logic circuit provided with various functions achieve various required performances and several Can have functions. The semiconductor device with these Benefits can be created by simple steps.

Since the logic circuit area and the three tubs in the Spei cell area can be formed simultaneously, the Number of masks required and the number of maskies steps are reduced.

In the memory cell area and in the logic circuit area can surround the n-wells of the three-well structures p-tubs are formed in different steps, to create different concentration distributions fen. Accordingly, the nMOS transistors with ver different characteristics are formed, the Vorrich device can be created with several functions.

In general, a transistor formed in a well having an impurity concentration peak at a great depth from the surface of the semiconductor substrate must be spaced a certain distance from the end of the well in order to suppress the deterioration of the transistor characteristics. However, in the semiconductor device according to the second embodiment, the n-wells 331 and 352 are spaced from the p-wells 41 and 43 , respectively, so that the semiconductor device can be further miniaturized.

Third embodiment

Fig. 28 shows a semiconductor device according to a third embodiment of the invention, which is for example provided with a logic circuit, memory cells and a peripheral circuit. Although not shown, pMOS transistors are formed in the n-wells 33 , 34 , 351 and 36 for the respective purposes, while nMOS transistors are formed in the p-wells 41-44 for the respective purposes. In some cases, no transistor is formed in the n-wells 33 and 351 . The n-wells 33 and 332 surround the p-well 41 together with the n-well 321 (lower n-well), while the n-wells 351 and 311 surround the p-well 43 together with the n-well 31 (lower n Tub) surrounded. In this way, the p-wells 41 and 43 are electrically insulated from the other sections, the three-well structure as described above being created.

Fig. 29 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the third imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-wells 33 (or 351), 332 and 321 in both the semiconductor substrate 1 in a section along the line NN in Fig. 28. As shown in Fig. 29, the n-well 33 (or 351 ) contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the peak of its impurity concentration is at a depth of about 0.5-0.8 µm from the surface of the semiconductor substrate. The n-well 332 contains the impurities such as phosphorus with about 1 × 10 ^16-1 × 10 ¹⁸ cm ^-3 , the tip of its impurity concentration at a depth of about 1-1.5 microns from the surface of the semiconductor substrate . The n-well 321 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration being at a depth of about 2-2.5 μm from the surface of the semiconductor substrate .

Fig. 30 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the third imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-wells 321 and 332 in the p-well 41 and the semiconductor substrate 1 in a section along the Line OO in Fig. 28. As shown in Fig. 30, the n-well 321 contains the n-type impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip of its impurity concentration in a depth of about 2-2.5 microns from the upper surface of the semiconductor substrate. The n-well 322 contains the impurities such as phosphorus with about 1 × 10 ¹⁶ -1 × 10 ¹⁸ cm ^-3 , the tip of its impurity concentration being at a depth of about 1-1.5 μm from the surface of the semiconductor substrate . The p-well 41 contains the impurities such as boron with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration at a depth of about 0.5-0.8 μm from the surface of the semiconductor substrate lies. Further, FIG. 30, the Störstellenkonzen trationsverteilung in one (in Fig. 28, not shown) nalsperrschicht Ka, which contains the impurities such as boron at about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3, wherein the Störstellenkonzen trationsspitze at a depth of about 0.2-0.5 microns from the semiconductor substrate surface.

Fig. 31 is a graph of the distributions of impurity concentrations in the semiconductor device according to the third embodiment of the invention, and more specifically of the impurity concentrations in the n-well 31 , in the p-well 43 and in the semiconductor substrate 1 in a section along the line PP in Fig. 28. As shown in Fig. 31, the n-well 31 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip of its impurity concentration at a depth of about 2-2.5 microns from the surface of the semiconductor substrate. The p-well 43 contains the impurities such as boron with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the peak of its impurity concentration being at a depth of about 1-1.5 μm from the surface of the semiconductor substrate. As a result of the implantation of the impurities in the p-well 43 to form the n-well 311 , the concentration peak of the impurities such as phosphorus in the substrate is formed at substantially the same depth as the impurity concentration peak of the p-well 43 . In this section, however, the concentration of p-type impurities is sufficiently higher than that of n-type impurities. This means that no leakage current can occur.

The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that in the memory cell region in a portion that lies between the n-well 351 formed in a flat layer and the n-well 31 and its impurity concentration in the depth direction of the Substrate sinks, the n-well 311 is formed, while in the logic circuit area in a section that lies between the n-well (lower n-well) 321 and the n-well 33 formed in a deep position and its impurity concentration in Depth direction of the substrate drops, the n-well 332 is formed to compensate for the impurity concentration. Except for the above, the structures are the same as in the semiconductor device of the first embodiment. The three-well structure in either the logic circuit area or the memory cell area of the third embodiment can be replaced by the three-well structure in the first or second embodiment.

According to the semiconductor device of the third embodiment the deterioration of element characteristics such as that Increase in leakage current across the pn junction between the Semiconductor substrate (the tub) and the source / drain region in a portion in the memory provided with the capacitor are suppressed even in the case that the depth of the tub according to the reduction in insulation width and the tub width because of the miniaturization of the integrated semiconductor device is reduced, the Refresh characteristics can be improved.

The transistor in the DRAM memory cell area is in the deep p-tub surrounded by the n-tub. Thereby can set the potential regardless of the substrate and a soft error can be suppressed.

Since the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the while the potential on the three tubs is independent can be set so that even those with the Transisto logic circuit with various functions achieve various required performances and several Can have functions.

The following is a method of making the semi-lead device according to the third embodiment of the invention described.

First, the insulation insulating film 2 and the silicon oxide film 24 are formed on the surface of the semiconductor substrate 1 similarly to the first embodiment. A photoresist mask 308 with openings is then formed over the surface of the region in which the triple well structure is formed and on the entire surface masked with the photoresist mask 308 under the conditions of about 2-10 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^{-2 performed} a high-energy implantation of the n-impurities such as phosphorus. The n-wells 31 and 321 are then formed. Furthermore, under the conditions of about 500 keV-3 MeV and about 1 × 10 ¹¹ -1 × 10 ¹³ cm ^-2, high energy implantation of the n-type impurities such as phosphorus is carried out. The n-wells 311 and 332 are thereby formed. Fig. 32 shows a sectional structure of the elements of the semiconductor device after completion of the above step. The photoresist mask 308 is then removed.

The p-wells 41-44 and the n-wells 33 , 34 , 351 and 36 are trained similarly to the first and second embodiments. Then the necessary elements are formed similar to the first embodiment.

The n-well 36 can be formed in the step of forming the n-wells 33 , 34 and 351 and thus simultaneously with them. In this case, the n-well 36 has the same concentration distribution as the n-wells 33 , 34 and 351 . If the training in the same step as described above is permissible, it can be achieved that the mask for forming the n-well 36 and the ion implantation step can be omitted using them.

In the method for forming the semiconductor device of the third embodiment, the n-wells 321 , 332 and 311 are formed in a different manner than in the method for manufacturing the semiconductor device of the first embodiment. Except for the above, the structures are formed in the same manner as in the first embodiment. The order of formation of the respective wells and the interconnection structure can be changed similarly to the first embodiment, and the three-well structure in either the logic circuit area or the memory cell area of the third embodiment can be replaced by the three-well structure in the first or second embodiment.

The semiconductor device with the well structure shown in FIG. 28 is formed in the manner described above.

According to the method of manufacturing the semiconductor device the third embodiment can the tub in the memory cell area formed even then with a great depth when the depth of the tub is reduced according to the Isolation width and the tub width because of the miniaturization tion of the semiconductor integrated circuit is reduced. Accordingly, the deterioration of the element characteristics such as rising leakage current across the pn junction between the semiconductor substrate (the tub) and the Source / drain area are suppressed, thus refreshing properties can be improved.

Since the p-well provided with the transistor in the memory cell area is surrounded by the lower n-well, this can Potential can be set independently of the substrate, whereby the soft error in the forth in the above procedure set semiconductor device is suppressed.

Because the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the while the potential on the three tubs is independent can be set so that even those with the Transisto logic circuit with various functions achieve various required performances and several Can have functions. The semiconductor device with these Advantages can be achieved by the simple steps  the.

The p-tubs of the three-tub structure surrounded by the n-tubs structures in the memory cell area and in the logic circuit areas can be trained in different steps to create different concentration distributions fen. Accordingly, the nMOS transistors with ver different characteristics are formed, the Vorrich device can be created with several functions.

The lower n-well formed on the underside of the p-well in the three wells of the logic circuit area is formed simultaneously with the n-well which is formed on the side of the p-well in the three wells of the memory cell area. Furthermore, the concentrations of the n-wells 332 and 311 are controlled. As a result, the n-wells 31 and 321 can be formed simultaneously with the n-wells 311 and 332 with the single photoresist mask, so that the number of required masks and the number of masking steps can be reduced.

Fourth embodiment

Fig. 33 is a cross section of a semiconductor device according to a fourth embodiment.

Fig. 33 shows an example of the semiconductor device with the logic circuit, the memory cells and the peripheral circuit. Although not shown, pMOS transistors are formed in the n-wells 33 , 34 , 351 and 36 for the respective purposes, while nMOS transistors are formed in the p-wells 41-44 for the respective purposes. In some cases, no transistor is formed in the n-wells 33 and 351 . The underside of the p-well 43 lies at a depth at which the impurity concentration of the n-well 312 is higher than that of the semiconductor substrate 1 . Between the n-wells 351 and 312 and between the n-wells 33 and 322, there are areas in which the concentration of the impurities such as phosphorus contained in the n-well is higher than the concentration of the impurities contained in the semiconductor substrate 1 such as boron is so that p-type semiconductors are formed. Each region that forms the p-type semiconductor has a small width of up to about 0.2 μm in the depth direction and also a low impurity concentration, so that the n-wells 33 and 322 are electrically connected to one another to form the three-well structure to train.

Fig. 34 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the fourth imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-well 33 (or 351) in the n-well 332 and the semiconductor substrate 1 in a section along line QQ in Fig. 33. As shown in Fig. 34, the n-well 33 (or 351 ) contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip its impurity concentration is at a depth of about 0.5-0.8 µm from the surface of the semiconductor substrate. The n-wells 31 and 331 contain the n-impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration at a depth of about 2-2.5 μm from the surface of the semiconductor substrate.

Fig. 35 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the fourth imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-well 312, in the p-well 43 and in the semiconductor substrate 1 in a section along the line RR in Fig. 33. As shown in Fig. 35, the n-well 312 contains the n-impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , with the tip of its impurity concentration at a depth of about 2-2.5 microns from the surface of the semiconductor substrate. The p-well 41 contains the impurities such as boron with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration at a depth of about 0.5-0.8 μm from the surface of the semiconductor substrate lies. Further, FIG. 35, the Störstellenkonzen trationsverteilung in one (in Fig. 33, not shown) nalsperrschicht Ka, which contains the impurities such as boron at about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3, wherein the Störstellenkon zentrationsspitze at a depth of about 0.2-0.5 microns from the semiconductor substrate surface.

The semiconductor device according to the fourth embodiment differs from the semiconductor device of the second embodiment in that in the fourth embodiment the n-well 352 from the second embodiment is not used. Except for the above, the structures are the same as in the semiconductor device of the second embodiment. The three-well structure either in the logic circuit area or in the memory cell area of the fourth embodiment can be replaced by the three-well structure in either the first, the second or the third embodiment.

According to the semiconductor device of the fourth embodiment the deterioration of element characteristics such as that Increase in leakage current across the pn junction between the Semiconductor substrate (the tub) and the source / drain junction in a section provided with the capacitor in the Memory cell area can be suppressed even if the Depth of the tub according to the reduction in insulation width and the tub width due to the miniaturization of the inte ized semiconductor circuit is reduced, with the Auf fresh data can be improved.  

The transistor in the DRAM memory cell area is in the of of the lower n-well surrounding deep p-well. This enables the potential to be switched on regardless of the substrate and a soft error can be suppressed.

Because the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the, the potential on the three tubs independently can be set so that even with the transistors logic circuit provided with various functions achieve various required performances and several Can have functions.

The following is a method of making the semi-lead device according to the fourth embodiment of the invention described.

First, the insulation insulating film 2 and the silicon oxide film 24 are formed on the surface of the semiconductor substrate 1 similarly to the first embodiment. Thereupon, a photoresist mask with openings is formed over the surface of the region in which the three-well structure is formed, and on the entire surface masked with the photoresist mask under the conditions of about 2-10 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^{-2 performed} a high-energy implantation of the n-impurities such as phosphorus. As a result, who formed the n-wells 311 and 332 . The p-wells 41-44 and the n-wells 33 , 34 , 351 and 36 are formed similarly to the second embodiment. Thereafter, the necessary elements are formed similarly to the first embodiment.

The n-well 36 can be formed in the step of forming the n-wells 33 , 34 and 351 and thus simultaneously with them. In this case, the n-well 36 has the same concentration distribution as the n-wells 33 , 34 and 351 . If formation in the same step is permissible as described above, it can be achieved that the mask for forming the n-well 36 and the ion implantation step can be omitted using them.

According to the method of manufacturing the semiconductor device the fourth embodiment, the tub in the memory cell area even then formed to a great depth when the depth of the tub is reduced according to the Isolation width and the tub depth because of the miniaturization tion of the semiconductor integrated circuit is reduced. Accordingly, deterioration of the element characteristics such as an increase in leakage current across the pn junction between the semiconductor substrate (the tub) and the Source / drain area are suppressed, thus refreshing properties can be improved.

Since the p-well provided with the transistor in the memory cell area is surrounded by the lower n-well, this can Potential set independently of the substrate and the soft one Error in the manufactured with the above procedure Semiconductor device can be suppressed.

Because the tub in the logic circuit area in a flat Location can be formed, the circuit miniaturi based and the potential on the three tubs turned on independently are so that even with the transistors different functions provided logic circuit achieve the required performance and multiple functions can have one. The semiconductor device with these advantages len can be made through the simple steps.

The one on the bottom of the p-tub in the three tubs of the Logic circuit area formed lower n-well is by  single execution of the implantation simultaneously with the on the side of the p-tub in the three tubs of the storage cell len-trained n-well. This can the number of masks required and the number of masks steps are reduced.

The p-tubs of the three-tub structure surrounded by the n-tubs structures in the memory cell area and in the logic circuit area trained in different steps to different concentration distributions create. Accordingly, nMOS transistors with ver different characteristics are formed, the Vorrich device can be created with several functions.

Fifth embodiment

Fig. 36 is a cross section of a semiconductor device according to a fifth embodiment.

Fig. 36 shows an example provided with the logic circuit, the memory cells and the peripheral circuit semiconducting tervorrichtung. Although not shown, 37 pMOS transistors are formed in the n-well for the respective purposes, while in the p-wells 41-44 nMOS transistors are formed for the respective purposes. However, one or some of these wells are not provided with a transistor, and are used only for the purpose of interacting with the lower n-well 31 (or 321 ) in order to make the p-well 41 (or 43 ) opposite the semiconductor substrate 1 electrically isolate. The underside of the p-well 43 lies at a depth in which the n-well 312 has a higher impurity concentration than the semiconductor substrate 1 .

Fig. 37 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the fifth imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-well 31 (or 321) in the n-well 37 and in the semiconductor substrate 1 in a section along line SS in Fig. 36. As shown in Fig. 37, the n-wells 31 and 321 contain the n-impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , wherein the peak of its impurity concentration is at a depth of about 2-2.5 µm from the surface of the semiconductor substrate. The n-well 37 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration at a depth of about 0.7-1.2 μm from the surface of the semiconductor substrate lies.

Fig. 38 is a graph of the distributions of Störstellenkonzen concentrations in the semiconductor device according to the fifth imple mentation of the invention, and more precisely the Störstellenkonzen trationsverteilungen in the n-well 37 and in Halbleitersub strat 1 in a section along the line TT in Fig. 36. As as shown in Fig. 38, the n-well 37 contains the Störstel len such as phosphorus at about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3, wherein the tip of its impurity concentration in a depth of about 0.7-1, 2 µm from, the surface of the semiconductor substrate.

The semiconductor device according to the fifth embodiment differs from the semiconductor device of the second embodiment in that the n-wells 352 and 331 from the second embodiment are not used in the fifth embodiment, while the n-well 37 with the impurity concentration peak in a lower position than the p-well 41 and in a flatter position than the p-well 43 . Except for the above, the structures are the same as those of the semiconductor device of the second embodiment.

According to the semiconductor device of the fifth embodiment the deterioration of element characteristics such as that Increase in leakage current across the pn junction between the Semiconductor substrate (the tub) and the source / drain region in a portion in the memory provided with the capacitor cell area are suppressed even if the Depth of the tub according to the reduction in the insulation width and the tub width due to the miniaturization of the inte grated semiconductor circuit is reduced, thereby reducing the on freshness properties can be improved.

The transistor in the DRAM memory cell area is in the deep p-tub surrounded by the lower n-tub. This enables the potential to be switched on regardless of the substrate and a soft error can be suppressed.

Because the tub in the logic circuit area in a flat Location is formed, the circuit can be miniaturized the, the potential on the three tubs independently can be set so that even with the transistors logic circuit provided with various functions achieve various required performances and several Can have functions.

The fact that the n-well with the concentration peak in egg ner greater depth than that with the memory cell transistor provided p-tub and at a smaller depth than the p- Well is provided in the logic circuit area, the Semiconductor device can be created that miniaturized is and can suppress the leakage current.

The following is a method of making the semi-lead device according to the fifth embodiment of the invention described.  

Fig. 39 is a sectional view of a step in the method of manufacturing the semiconductor device according to the fifth embodiment.

First, the insulation insulating film 2 and the silicon oxide film 24 are formed on the surface of the semiconductor substrate 1 similarly to the first embodiment. Then, similarly to the second embodiment, a photoresist mask is formed with an opening over the surface of the area in which the three-well structure is formed, and on the entire surface masked with the photoresist mask under the conditions of about 2-10 MeV and about 1 × 10 ¹² - 1 × 10 ¹⁴ cm ^{-2 performed} a high-energy implantation of the n-impurities such as phosphorus. The n-wells 31 and 321 are thereby formed.

Then, as shown in Fig. 39, a photoresist mask 307 with an opening is formed over the surfaces of the n-well formation areas in the logic circuit area, in the memory cell area and in the periphery, and under the entire surface masked with the photoresist mask the conditions of about 300 keV-2 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^{-2 performed} a high-energy implantation of the n-type impurities such as phosphorus. As a result, the n-well 37 is formed. Fig. 39 is a cross section of the ele ments of the semiconductor device after completion of the above genann th step.

The p-wells 41-44 and the required elements are designed similarly to the second embodiment. The order of the formation of the p- and n-tubs is not limited.

According to the method of manufacturing the semiconductor device the fifth embodiment, the tub in the memory  cell area even then formed to a great depth when the depth of the tub is reduced according to the Isolation width and the tub width because of the miniaturization tion of the semiconductor integrated circuit is reduced. Accordingly, deterioration of the element characteristics such as an increase in leakage current across the pn junction between the semiconductor substrate (the tub) and the Source / drain area can be suppressed, causing the on freshness properties can be improved.

Since the p-well provided with the transistor in the memory cell area is surrounded by the lower n-well, this can Potential can be set and a regardless of the substrate soft error in the forth in the above procedure set semiconductor device can be suppressed.

Because the p-well in the logic circuit area is in a flat Location can be formed, the circuit miniaturi be siert, while the potential on the three tubs can be set so that even those with the Logic with different functions circuit achieve various required performances and can have multiple functions. The semiconductor device with These benefits can be obtained through the simple steps be put.

The one on the bottom of the p-tub in the three tubs of the Logic circuit area trained lower n-well trained simultaneously with the n-tub that is on the side the p-well in the three wells of the memory cell area is formed, with only one implantation performed becomes. This allows the number of required masks and the number of masking steps can be reduced.

The p- surrounded by the n-wells of the three-well structures  Wells in the memory cell area and in the logic scarf area can be trained in different steps different concentration distributions create. Accordingly, the nMOS transistors can different characteristics are formed, the Vor direction with multiple functions can be created.

The fact that the n-well with the concentration peak in egg ner greater depth than that with the memory cell transistor provided p-tub and at a smaller depth than the p- Well is provided in the logic circuit area, the Semiconductor device can be created that miniaturized is and can suppress the leakage current.

Sixth embodiment

Fig. 40 is a cross section of a semiconductor device according to a sixth embodiment.

As shown in FIG. 40, a semiconductor substrate 111 contains p-type impurities such as boron with about 1 × 10 ¹⁹ cm ³ and is provided on its surface with an epitaxial layer 112 with a thickness of about 2.5-8.0 μm. Except that the n-wells 37 and 321 and the p-wells 41-44 are formed in the epi-taxi layer 112 , the semiconductor device 111 has substantially the same structure as the semiconductor device of the fifth embodiment.

Fig. 41 is a graph of the impurity concentration distributions in the semiconductor device according to the sixth embodiment of the invention, and more specifically the impurity concentration distributions in the n-well 31 , the p-well 43 , the epitaxial layer 112 and the semiconductor substrate 111 in a section along the line UU in Fig. 40. As shown in Fig. 41, the n-well 31 contains the impurities such as phosphorus with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the peak of its impurity concentration in one Depth of about 2-2.5 microns from the surface of the semiconductor substrate. The p-well 43 contains the impurities such as boron with about 1 × 10 ¹⁷ -1 × 10 ¹⁹ cm ^-3 , the tip of its impurity concentration being at a depth of about 1-1.5 μm from the upper surface of the semiconductor substrate . The thickness of the epitaxial layer 112 is preferably minimized, but a distance of approximately 0.5 μm or more from the boundary between the epitaxial layer 112 and the semiconductor substrate 111 to the impurity concentration peak of the n-well 31 must be observed.

The structure has been described in which the semiconductor device in the fifth embodiment is formed on the surface of the epitaxial layer 112 formed on the heavily doped semiconductor substrate 111 . If the relationships regarding the impurity distribution between the semiconductor substrate 111 , the epitaxial layer 112 and the n-well 31 are satisfied, however, similar effects can be achieved with the structure including the semiconductor device in any one of the first to fourth embodiments.

According to the semiconductor device of the sixth embodiment the semiconductor substrate has a high impurity concentration and can suppress the engagement. So there can be a distance between the source / drain regions of the neighboring pMOS and nMOS transistors decreased and the semiconductor device thereby be further miniaturized.

Because the transistors on the surface of the epitaxial layer are formed, the gate insulating film can be the improved one Have reliability.

The following is a method of making the semi-lead  device according to the sixth embodiment of the invention described.

Fig. 42 is a graph of Störstellenkonzentrationsverteilun gen an epitaxial wafer (ie, a wafer having formed on the surface of the semiconductor substrate 111 Epita xieschicht 112) prior to forming the wells and the elements according to the sixth embodiment. The wells and the elements are formed on the surface of the epitaxial layer 112 in a similar manner as in the fifth embodiment, so that the semiconductor device shown in FIG. 40 is completed. However, the impurities contained in the semiconductor substrate 111 diffuse through various heat treatments for forming the insulation insulating film, etc. Accordingly, the structure in the state of the epitaxial wafer differs from the semiconductor substrate shown in FIG. 40 with respect to the distribution of the impurities contained in the semiconductor substrate 111 and in the epitaxial layer 112 . The heat treatments to be carried out in the manufacturing steps depend on the elements to be trained. If the heat treatment is carried out frequently, a large amount of the impurities contained in the semiconductor substrate 111 tend to diffuse into the epitaxial layer 112 , so that the thickness of the epitaxial layer 112 must be controlled according to the heat treatment.

According to the method of manufacturing the semiconductor device the sixth embodiment has the semiconductor substrate a high impurity concentration and can latch suppress. Thus, a distance between the Source / drain regions of the neighboring pMOS and nMOS transi can be reduced, thereby reducing the semiconductor device can be further miniaturized.

Because the transistors on the surface of the epitaxial layer  can be formed, the gate insulating film can be the improved one Have reliability.

Seventh embodiment

Fig. 43 is a cross section of a semiconductor device according to a seventh embodiment.

Fig. 43 shows an example of a semiconductor device to the logic circuit, the memory cells and the peripheral TIC. The memory cell area is provided with the p-well 431 , which has the same impurity concentration as the p-wells 41 and 42 in the logic circuit. In the memory cell area, the memory cell transistors are formed in the p-well 43 , while the other transistors are formed in the p-well 431 . Except for the above, the structures are the same as in the first embodiment.

Fig. 44 is a plan view of the semiconductor device according to the seventh embodiment of the invention. Fig. 43 shows a cross section along the line VV in Fig. 44. In Fig. 44 a of the dotted line a surrounded portion of the n-well 32 in a greater depth than the p-well 41 and the n-well 33 is provided . A section surrounded by the broken line b with the n-well 31 is provided at a greater depth than the p-wells 43 and 431 and the n-well 35 . The p-wells 43 and 431 are electrically insulated from the semiconductor substrate 1 .

Although the description is compared to the first embodiment form has been given, similar effects can also be achieved the structure in which the semiconductor device tion of any one of the first to sixth embodiments is formed.  

According to the semiconductor device of the seventh embodiment apart from the memory cell, the nMOS transistors can oil transistors are formed in the memory cell area, while the leakage current is suppressed by the fact that the Spei cher cell transistor in the p-well with an impurity con centering tip trained to a sufficient depth det. Refresh characteristics are also improved. The impurity concentration peak with that of the other tran transistors as p- provided with the memory cell transistors Pan lies at a much smaller depth, which makes the oil sistor itself in the section near the tub end can be designed so that further miniaturization the structure can be achieved while a deterioration transistor characteristic data is suppressed.

In accordance with the p-well 44 formed in the peripheral circuit area, all of the p-wells apart from the p-well 43 have flat impurity concentration distributions, whereby the transistors in the areas other than the memory cell area also in the portion near the well end can be formed so that further miniaturization of the structure can be achieved while suppressing deterioration of the transistor detection data.

The following is a method of making the semi-lead device according to the seventh embodiment of the invention described.

Fig. 45 is a sectional view of a step in a method for manufacturing the semiconductor device according to the seventh embodiment. In Fig. 45, 310 denotes a photoreactive sistmaske.

Similar to the first embodiment, the insulation insulating film 2 and the silicon oxide film 24 are formed on the surface of the semiconductor substrate 1 . Then the n-wells 31 , 32 , 35 and 36 and the p-wells 43 and 44 are trained.

Then, as shown in FIG. 45, a photoresist mask 310 is formed. The photoresist mask 310 has openings in the logic circuit area and the peripheral area over the surfaces of the p-well formation areas, while in the memory cell area over the surfaces of the p-well areas where the nMOS transistors different from the memory cell transistors are formed, openings possesses. A high energy implantation of p-type impurities such as boron is performed on the entire surface masked with the photoresist mask 310 under the conditions of about 150 keV-1 MeV and about 1 × 10 ¹² -1 × 10 ¹⁴ cm ^-2 . As a result, the p-wells 41 , 42 and 431 are formed. Fig. 44 is a cross section of the elements of the semiconductor device after completion of the above step. The p-well 44 can be formed simultaneously in the above structure, whereby the p-well 44 can be formed in a smaller depth and miniaturization can be achieved. The photoresist mask 310 is then removed.

Furthermore, the elements become similar to the first embodiment educated. The order of training the p-tubs and the n-tubs are not limited.

According to the method of manufacturing the semiconductor device In the seventh embodiment, the memory cell oil transistors in the memory cell area nMOS transistors are formed, making the following Advantages are achieved. Since the one with the above from the memory cell transistor different nMOS transistor  provided p-well at the same time as the p-well in the logic circuit area is formed, the fault location con centering peak of the p-well in the memory cell area can be changed by simple steps, both the Suppression of leakage current as well as miniaturization can be achieved at the same time.

Eighth embodiment

Fig. 46 is a cross section of a semiconductor device according to an eighth embodiment of the invention.

Fig. 46 shows an example of the semiconductor device to the logic circuit, rieschaltung to the memory cells and the Periphe. Even in the memory cell area, the memory cell transistor is formed in the p-well 43 , while the transistors different from the memory cell transistor are formed in a p-well 432 . The p-well 432 has the same impurity concentration distribution as the p-wells 41 and 42 in the logic circuit area, while all of the p-wells different from the p-wells 43 and 44 have the same impurity concentration distributions.

Fig. 47 is a plan view of a semiconductor device according to an eighth embodiment of the invention. FIG. 46 shows a section along the line WW in FIG. 47. For reasons of simplicity, FIG. 47 does not show the insulating insulating film 2 . As shown in FIG. 47, a portion surrounded by the broken line a with the n-well 32 is provided lower than the p-well 41 and the n-well 33 . A section surrounded by the broken line b is provided with the n-well 31 lower than the p-well 43 and the n-well 35 . The p-wells 41 and 43 are electrically insulated from the semiconductor substrate 1 . The p-well 432 surrounds the p-well 43 so that the p-well 43 is not adjacent to the n-well 35 . Except for the above, the structures are the same as in the seventh embodiment.

In the figures, the p-well 44 in the peripheral circuit area has the same impurity distribution as the p-well 43 , but may have the same impurity distribution as the p-well in the logic circuit area.

Although the description has been given in comparison with the seventh embodiment, similar effects can be achieved even by the structure in which the above p-well 432 is used in any one of the first to sixth embodiments.

Fig. 48 is a plan view of the semiconductor device according to the eighth embodiment of the invention, which in Fig. 44 gezeig th seventh embodiment of the isolation insulating film 2 does not show in a plan view of the semiconductor device according to. In the seventh embodiment, the p-wells 43 and 432 with different impurity concentration distributions are subjected to ion implantation using different photoresist masks, respectively. Thus, the displacement of the mask or the like may result in a situation in which the p-impurities are implanted twice in the edge portion between the p-wells 43 and 432 , the impurity concentration in the edge portion being particularly high. In the sections in the circles denoted by "e", the above situation leads to the formation of the high-concentration pn junction with the n-impurities contained in the n-well 35 . A leakage current thus flows, where the characteristic data of the memory cell transistor formed in the p-well 43 deteriorate. In the semiconductor device according to the eighth embodiment, the p-well 43 provided with the memory cell transistor is surrounded by the p-well 432 , whose impurity concentration distribution is similar to that of the p-wells 41 and 42 , and in the logic circuit area, etc., ie in the areas different from the storage cell area. Thus, no leakage current can flow due to the direct contact of the n-well 35 with the high concentration portion due to the overlap of the ion implantation in the p-wells 43 and 432 . Accordingly, the characteristics of the memory cell transistor formed in the p-well 43 are improved.

The following is a method of making the semi-lead device according to the eighth embodiment of the invention described.

Except that when the ion implantation is performed to form the p-wells 41 and 42, the ion implantation is also performed on the area of the p-well 432 shown in FIG. 47, the semiconductor device according to the eighth embodiment can be similar to the semiconductor device of the seventh embodiment.

According to the method of manufacturing the semiconductor device of the eighth embodiment, the semiconductor device can be provided in which in the logic circuit area and in other areas, that is, in areas other than the memory cell area, the p-well 43 provided with the memory cell transistor from the p-well 432 is surrounded with a similar impurity concentration as the p-wells 41 and 42 . Even if the section with a high concentration is formed because of the overlap of the ion implantation in the p-wells 43 and 432 , there is therefore no possibility of direct contact with the n-well and thus of the leakage current occurring. Accordingly, the method can provide the semiconductor device in which the memory cell transistor formed in the p-well 43 has the improved characteristics.

Fig. 49 is a plan view of another Halbleitervorrich processing according to the eighth embodiment. In Fig. 49, the insulating film 2 is not shown for the sake of simplicity. As shown in Fig. 49, the impurity implantation for forming the p-well 432 and the impurity implantation for forming the p-well 43 can both be performed on a hatched portion f, so that the hatched portion f can have a high concentration . If the ion implantation is carried out in such a way that the overlap in the p-wells 43 and 432 is prevented, a situation can occur because of the displacement of a mask in which the p-impurities in a certain section in the hatched section f do not be implanted, a pnp transition being formed because of the n-impurities in the n-well 31 implanted in the section indicated by the dash line b and because of the p-impurities in the wells 43 and 432 . However, the presence of the hatched portion f eliminates the possibility of forming the pnp junction and improves the characteristics of the memory cell transistor formed in the p-well 43 .

Although the invention has been described and shown in detail , of course, this only serves as an explanation Example and should not be understood as a limitation be, the inventive concept and the scope of Erfin only limited by the appended claims are.

Claims (20)

1. semiconductor device comprising:
a semiconductor layer ( 1 ) of a first conductivity type;
a first impurity region ( 31 , 312 ) of a two-th conductivity type, which is formed on a main surface of the semiconductor layer ( 1 ) and has a first impurity concentration peak;
a second impurity region ( 43 ) of the first conduction type formed on the main surface of the semiconductor layer ( 1 ), being in a flat region provided with the first impurity region ( 31 , 312 ) and a second impurity concentration peak in a small one Depth as the first impurity concentration peak;
a third impurity region ( 35 ) of the second conduction type, which is formed on the main surface of the semiconductor layer ( 1 ) and lies in the flat region provided with the first impurity region ( 31 , 312 ) and surrounds the second impurity region ( 43 ) , and has a third impurity concentration peak at a depth less than the first impurity concentration peak;
a fourth impurity region ( 32 , 322 ) of the second conductivity type formed on the main surface of the semiconductor layer ( 1 ), being in an area spaced from the first impurity region ( 31 , 312 ) and having a fourth impurity concentration peak;
a fifth impurity region ( 41 ) of the first conduction type, which is formed on the main surface of the semiconductor layer ( 1 ), it lies in a flat region provided with the fourth impurity region ( 32 , 322 ) and a fifth impurity concentration peak in a small ren Depth than the second and fourth impurity concentration peaks;
a sixth impurity region ( 33 ) of the second conductivity type, which is formed on the main surface of the semiconductor substrate, being located in a flat region provided with the fourth impurity region ( 32 , 322 ), surrounding the fifth impurity region ( 41 ) and a sixth impurity concentration peak at a depth less than the fourth impurity concentration peak;
a first field effect element of the second conduction type, which is formed on the main surface of the second impurity region ( 43 ); and
a second field effect element of the second line type, which is formed on the main surface of the fifth Störstellege area ( 41 ). 2. Semiconductor device according to claim 1, characterized in that the first impurity concentration peak and the fourth impurity concentration peak are formed in wesentli chen at the same depth from the main surface of the semiconductor layer ( 1 , 111 ). 3. A semiconductor device according to claim 2, characterized in that the first and the third Störstellenge area ( 312 , 351 ) in a depth direction determined by the main surface of the semiconductor layer ( 1 ) are spaced apart from one another by a specific distance, while the fourth and that sixth impurity region ( 322 , 33 ) in the depth direction determined by the main surface of the semiconductor layer ( 1 ) are spaced apart by a predetermined distance. 4. Semiconductor device according to claim 2 or 3, characterized by:
a seventh impurity region ( 352 ) of the second conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ), being located in a flat region provided with the first impurity region ( 31 ), surrounding the second impurity region ( 43 ) and a seventh Impurity concentration peak which is flatter than the first impurity concentration peak and lower than the third impurity concentration peak and has a lower concentration than the first and third impurity concentration peak; and
an eighth impurity region ( 331 ) of the second line type formed on the main surface of the semiconductor layer ( 1 ), being located in an area provided with the fourth impurity region ( 32 ), surrounding the fifth impurity region ( 41 ) and one eighth impurity concentration peak, which is flatter than the fourth impurity concentration peak and lower than the sixth impurity concentration peak and has a lower concentration than the fourth and sixth impurity concentration peak. 5. Semiconductor device according to claim 2 or 3, characterized by:
a seventh impurity region of the second conduction type, which is formed on the main surface of the semiconductor layer ( 1 ), being in a flat region provided with the first impurity region ( 31 , 312 ), the second impurity region ( 43 ) with a predetermined distance surrounds therebetween, and has a seventh impurity concentration peak which is flatter than the first impurity concentration peak and lower than the third impurity concentration peak; and
a third field effect element of the first conduction type, which is formed in the third impurity region ( 35 ). 6. A semiconductor device according to any preceding claim, characterized in that the fourth impurity concentration tion peak flatter than the first impurity concentration is great.   7. A semiconductor device according to any preceding claim, characterized by:
a ninth impurity region ( 44 ) of the first conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ), in a region different from the first ( 31 , 312 ) and fourth ( 32 , 322 ) impurity region, and a ninth impurity concentration peak has substantially the same depth as the second impurity concentration peak;
a tenth impurity region ( 42 ) of the first conductivity type formed on the main surface of the semiconductor layer ( 1 ), in a region other than the first ( 31 , 312 ), fourth ( 32 , 322 ) and ninth ( 44 ) impurity region lies and has a tenth impurity concentration peak substantially at the same depth as the fifth impurity concentration peak;
an eleventh impurity region ( 34 ) of the second conductivity type formed on the main surface of the semiconductor layer ( 1 ), being in one of the first ( 31 , 312 ), fourth ( 32 , 322 ), ninth ( 44 ) and tenth ( 42 ) Impurity region is different region and has an eleventh impurity concentration peak at substantially the same depth as the fifth impurity concentration peak;
a twelfth impurity region of the second conduction type, which is formed on the main surface of the semiconductor layer ( 1 ), being in one of the first ( 31 , 312 ), fourth ( 32 , 322 ), ninth ( 44 ), tenth ( 42 ) and eleventh ( 34 ) impurity region is different region and has a twelfth impurity concentration peak substantially at the same depth as the second impurity concentration peak;
a third field effect element of the second conduction type formed on the main surface of the ninth ( 44 ) impurity region;
a fourth field effect element of the second conduction type formed on the main surface of the tenth ( 42 ) impurity region;
a fifth field effect element of the first conduction type formed on the main surface of the eleventh impurity region ( 34 ); and
a sixth field effect element of the first line type, which is formed on the main surface of the twelfth Störstellege area. 8. Semiconductor device according to one of claims 1 to 6, characterized by:
a ninth impurity region ( 44 ) of the first conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ), in a region different from the first ( 31 , 312 ) and fourth ( 32 , 322 ) impurity region, and a ninth impurity concentration peak has substantially the same depth as the second impurity concentration peak;
a tenth impurity region ( 42 ) of the first conductivity type formed on the main surface of the semiconductor layer ( 1 ), in a region other than the first ( 31 , 312 ), fourth ( 32 , 322 ) and ninth ( 44 ) impurity region lies and has a tenth impurity concentration peak substantially at the same depth as the fifth impurity concentration peak;
an eleventh impurity region ( 34 ) of the second conductivity type formed on the main surface of the semiconductor layer ( 1 ), being in one of the first ( 31 , 312 ), fourth ( 32 , 322 ), ninth ( 44 ) and tenth ( 42 ) Impurity site area is different area and has an eleventh impurity concentration peak;
a third field effect element of the second conduction type formed on the main surface of the ninth ( 44 ) impurity region;
a fourth field effect element of the second conduction type which is formed on the main surface of the tenth impurity region ( 42 ); and
a fifth field effect element of the first conduction type, which is formed on the main surface of the eleventh impurity region ( 34 ), wherein
the third, sixth and eleventh impurity concentration peaks are at substantially the same depth as the fifth impurity concentration peak. 9. The semiconductor device according to one of claims 2 to 8, characterized in that the third and sixth sturgeon peak concentration flatter than the second interfering point steering concentration peak and lower than the fifth disturbance steering concentration peaks are. 10. A semiconductor device according to claim 9, characterized by
an impurity region of the second conductivity type formed on the main surface of the semiconductor layer ( 1 ), being in a region different from the first and fourth regions ( 31 , 32 ), and an impurity concentration peak substantially at the same depth as the third and sixth impurity concentration peak; and
an element of the first conduction type that is formed in this impurity region. 11. A semiconductor device according to any preceding claim, characterized by
an impurity region of the first conductivity type formed on the main surface of the semiconductor layer ( 1 ), being in an area between the second impurity region ( 43 ) and the third impurity region ( 35 ) and having an impurity concentration peak which is shallower than the second Impurity concentration peak; and
an element of the second conduction type formed in this impurity area. 12. The semiconductor device according to any preceding claim, characterized by a further semiconductor layer (1) lying on another main surface of the semiconductor layer (1) and a higher impurity concentration than the semiconductor layer (1) has. 13. A semiconductor device comprising:
a semiconductor layer ( 1 ) of a first conductivity type;
a first impurity region ( 31 ) of a second conductivity type, which is formed on a main surface of the semiconductor layer ( 1 ) and has a first impurity concentration peak;
a second impurity region (43) processing type from the first Lei, which is det ausgebil on the main surface of the set square with the first sturgeon (31) semiconductor layer (1) provided, whereby it is fully constantly surrounded by the first impurity region (31) and a second Impurity concentration peak at a smaller depth than the first impurity concentration peak;
a third impurity region ( 432 ) of the first conduction type, which is formed on the main surface of the semiconductor layer ( 1 ) and lies in an region between the first ( 31 ) and the second ( 43 ) impurity region, the second impurity region ( 43 ) surrounds and has a third impurity concentration peak at a smaller depth than the second impurity concentration peak; and
a first field effect element of the second conduction type, which is formed on the main surface of the second fault location region ( 43 ). 14. The semiconductor device according to claim 13, characterized in that between the second impurity region ( 43 ) and the third impurity region ( 432 ) there is no impurity region of the second conduction type. 15. A semiconductor device according to claim 13 or 14, characterized by:
a fourth impurity region ( 44 ) of the first conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ), is located in an area different from the first impurity region ( 31 ) and a fourth impurity concentration peak substantially at the same depth as has the second impurity concentration peak;
a fifth impurity region ( 41 , 42 ) of the first conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ), being located in an area different from the first ( 31 ) and fourth ( 44 ) impurity regions, and a fifth impurity concentration peak with a has a smaller depth than the second and fourth impurity concentration peaks;
a sixth impurity region ( 33 , 34 ) of the second conductivity type formed on the main surface of the semiconductor layer ( 1 ), being different in one of the first ( 31 ), fourth ( 44 ) and fifth ( 41 , 42 ) impurity regions Area and has a sixth impurity concentration peak at substantially the same depth as the fifth impurity concentration peak;
a seventh impurity region ( 36 ) of the second conduction type formed on the main surface of the semiconductor layer ( 1 ), in a region other than the first ( 31 ), fourth ( 44 ) and sixth ( 33 , 34 ) impurity region lies and has a seventh impurity concentration peak substantially at the same depth as the fourth impurity concentration peak;
a second field effect element of the second conduction type which is formed on the main surface of the fourth impurity region ( 44 );
a third field effect element of the second conduction type, which is formed on the main surface of the fifth disturbance region ( 41 , 42 );
a fourth field effect element of the first conduction type formed on the main surface of the sixth impurity region ( 33 , 34 );
a fifth field effect element of the first conduction type formed on the main surface of the seventh impurity region ( 41 , 42 ); and
a capacitor connected to one of the source / drain regions of the first element. 16. The semiconductor device according to any one of claims 13 to 15, characterized by a further semiconductor layer which lies in a further major surface of the semiconductor layer (1) and a higher impurity concentration than the semiconductor layer (1) has. 17. A method of manufacturing a semiconductor device comprising the following steps:
Forming a first impurity region ( 31 ) of a second conductivity type with a first impurity concentration peak on a main surface of a semiconductor layer ( 1 ) of a first conductivity type;
Forming a second impurity region ( 32 ) of the second conduction type, which is arranged on the main surface of the semiconductor layer ( 1 ), lying in an area different from the first impurity region ( 31 ) and having a second impurity concentration peak;
Forming a third impurity region ( 43 ) of the first conductivity type, which is arranged on the main surface of the semiconductor layer ( 1 ) provided with the first impurity region ( 31 ) and which has a third impurity concentration peak at a smaller depth than the first impurity concentration peak;
Forming a fourth impurity region ( 41 ) of the first conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ) provided with the second impurity region ( 32 ) and has a fourth impurity concentration peak at a smaller depth than the second impurity concentration peak;
Forming a fifth impurity region ( 351 ) of the second conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ) provided with the first impurity region ( 31 ) and has a fifth impurity concentration peak at a smaller depth than the first and third impurity concentration peaks, and
Forming a sixth impurity region ( 33 ) of the second conductivity type, which is arranged on the main surface of the semiconductor layer ( 1 ) provided with the second impurity region ( 32 ), surrounding the fourth impurity region ( 41 ) and having the fifth impurity concentration peak;
Forming a first element of the second conduction type on the main surface of the third impurity region ( 43 ); and
Forming a second element of the second conduction type on the main surface of the fourth impurity region ( 41 ). 18. A method of manufacturing a semiconductor device according to claim 17, characterized by the following step:
Forming a seventh impurity region ( 352 ) of the second conductivity type, which is arranged on the main surface of the semiconductor layer ( 1 ), lying in a flat region provided with the first impurity region ( 31 ), surrounding the third impurity region ( 43 ) and one has a seventh impurity concentration peak that is flatter than the first impurity concentration peak and lower than the fourth impurity concentration peak and whose concentration is lower than that of the first and sixth impurity concentration peaks; and
Forming an eighth impurity region ( 331 ) of the second conductivity type, which is arranged on the main surface of the semiconductor layer ( 1 ), being located in an area provided with the second impurity region ( 32 ), surrounding the fourth impurity region ( 41 ) and the seventh Impurity concentration peak. 19. A method for producing a semiconductor device according to claim 17 or 18, characterized in that
the step of forming the third impurity region ( 43 ) comprises the step of forming a ninth impurity region ( 44 ) of the first conductivity type, which is disposed on the main surface of the semiconductor layer ( 1 ), in one of the first and second impurity regions ( 31 , 32 ) lies in a different area and has a ninth impurity concentration peak;
the step of forming the fourth impurity region ( 41 ) comprises the step of forming a tenth impurity region ( 42 ) of the first conductivity type, which is arranged on the main surface of the semiconductor layer ( 1 ), in one of the first ( 31 ), second ( 32 ) and ninth ( 44 ) impurity region is different region and has a tenth impurity concentration peak; and
the step of forming the fifth and sixth impurity regions ( 351 , 33 ) includes the step of forming an eleventh impurity region ( 36 ) of the second conductivity type, which is formed on the main surface of the semiconductor layer ( 1 ), in one of the first ( 31 ), second ( 32 ), ninth ( 44 ) and tenth ( 42 ) impurity area different area and has an eleventh impurity concentration peak. 20. A method of manufacturing a semiconductor device according to claim 19, characterized in that the fifth, sixth and eleventh impurity concentration peak shallower than the third impurity concentration peak and lower than that fourth impurity concentration peak lies.