DE4020219A1 - Mean value device for electronic measuring appts. - uses shift register outputs controlling sample-and-hold circuits coupled to adder - Google Patents

Abstract

The mean value device for electronic measuring appts. provides a continuous mean value from the analogue measured values, using a shift register (3), a clock generator (4), sample-and-hold circuits (1) and an adder (2). The shift register activates the individual sample-and-hold circuits (1) under control of the clock pulses, to transfer their outputs to the adder (2). The adder provides the mean value (9) at its output (A) with a delay time defined by the number of sample-and-hold circuits (1) divided by the clock pulse frequency. The delay time is adjustable by varying the frequency. USE - For feedback process control.

Description

Title of the invention

Device for constant averaging of an analog Measurand.

Field of application of the invention

The device advantageously takes place in electronic Measuring devices application for suppressing unwanted fluctuations against analog measured variables.

Characteristic of the known prior art

To suppress unwanted fluctuations and disturbances Analog measurands are either low-pass circuits or Di capital calculator applied. The low-pass post-circuits have that Disadvantage that considerable time Ver Measurement delays occur in certain applications conditions, especially in process control, may be too large. In many cases, the use of a digital computer is not necessary. In addition, the measured value is only available for digital computers available at certain times depending on the Time over which to average.

Aim of the invention

The aim of the invention is without filtering and without the one Set of digital computers to an averaging device Find.

Statement and nature of the invention

The object of the invention is to provide a device for permanent Finding the mean for an analog measured variable, the Delay time not longer than the period of the largest  fluctuation to be averaged. According to the task solved in that a circuit consisting of a slide register, a clock generator, a sample-and-hold scarf device and an adder, is arranged such that the Shift registers one by one the n-sample-and-hold scarf services clocked individually for passage. The outputs of the sample and-hold circuits are added in the adder. It there is therefore always a sample-and-hold circuit on continuity and n-1 sample-and-hold circuits Hold. Are all sample-and-hold circuits once switched through, this process begins after a quasi-rota principle again. The delay time for the device is adjustable and results from the relationship · N ist the number of sample-and-hold circuits and f is that Frequency.

Embodiment

The invention is illustrated below using an exemplary embodiment explained. The drawing shows:

Fig. 1 block diagram of the arrangement of the device for averaging.

The shift register 3 is set with the load inputs (P ₁ -P _n ) 6 so that one input is set to "one" and all others to "zero". With the unlocking 7 , the outputs (Q _l -Q _n ) 5 are placed on the mask set with the loading inputs 6 and the pushing begins.

First, the first "one" is pushed through all outputs 5 in time with the clock generator 4 . If this "one" has reached the output Q _n , the process begins again. The clock of the clock generator 4 is fed to the sliding register 3 via the clock input 8 . The shift register 3 now clocks through all the sample-and-hold circuits 1 individually, so that a circuit 1 is continuously switched to "pass" and n-1 circuits 1 are switched to "hold". If all circuits 1 are clocked through, the process begins again. At the output of the addi tion element 2 , the mean value 9 of the analog value is thus constantly present over a period of seconds (f being the frequency of the clock generator). The sample-and-hold circuit 1 is an analog value 10 entered via the second input. In the adder 2 , all outputs of the circuits 1 are added and reduced (n is the number of circuits 1 ).

Reference numerals

1 sample-and-hold circuit
2 adder
3 shift registers
4 clock generator
5 Q _1-n , outputs
6 pin _in , charging inputs
7 P _E , unlocking
8 C _p , clock input
9 A mean
10 analog value

Claims (2)

1. A device for constant averaging of an analog measurement, characterized in that a circuit consisting of a shift register ( 3 ), a clock generator ( 4 ), a sample-and-hold circuit ( 1 ) and an addition element ( 2 ) , is arranged such that the shift register ( 3 ) successively clocks the n-sample-and-hold circuits ( 1 ) individually for passage and adds the outputs of the sample-and-hold circuit ( 1 ) in the adder ( 2 ). 2. Device for constant averaging according to patent Claim 1, characterized in that the delay time the device is adjustable from seconds.