DE3889511D1 - Speicherung von Grenzzeitüberschreitungen und Quittungsantworten nach Ein-/Ausgabebefehlen. - Google Patents

Speicherung von Grenzzeitüberschreitungen und Quittungsantworten nach Ein-/Ausgabebefehlen.

Info

Publication number
DE3889511D1
DE3889511D1 DE3889511T DE3889511T DE3889511D1 DE 3889511 D1 DE3889511 D1 DE 3889511D1 DE 3889511 T DE3889511 T DE 3889511T DE 3889511 T DE3889511 T DE 3889511T DE 3889511 D1 DE3889511 D1 DE 3889511D1
Authority
DE
Germany
Prior art keywords
input
storage
time limits
output commands
acknowledgment responses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889511T
Other languages
English (en)
Other versions
DE3889511T2 (de
Inventor
Michael D Smith
Richard A Lemay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Application granted granted Critical
Publication of DE3889511D1 publication Critical patent/DE3889511D1/de
Publication of DE3889511T2 publication Critical patent/DE3889511T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE3889511T 1987-09-03 1988-09-02 Speicherung von Grenzzeitüberschreitungen und Quittungsantworten nach Ein-/Ausgabebefehlen. Expired - Fee Related DE3889511T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/092,863 US4872110A (en) 1987-09-03 1987-09-03 Storage of input/output command timeout and acknowledge responses

Publications (2)

Publication Number Publication Date
DE3889511D1 true DE3889511D1 (de) 1994-06-16
DE3889511T2 DE3889511T2 (de) 1994-12-15

Family

ID=22235532

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889511T Expired - Fee Related DE3889511T2 (de) 1987-09-03 1988-09-02 Speicherung von Grenzzeitüberschreitungen und Quittungsantworten nach Ein-/Ausgabebefehlen.

Country Status (5)

Country Link
US (1) US4872110A (de)
EP (1) EP0306043B1 (de)
AU (1) AU602238B2 (de)
CA (1) CA1308199C (de)
DE (1) DE3889511T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8800858A (nl) * 1988-04-05 1989-11-01 Philips Nv Rekenmachinesysteem voorzien van een hoofdbus en een tussen processor en geheugen direkt verbonden extra kommunikatielijn.
JPH03231320A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp マイクロコンピュータシステム
JPH04236682A (ja) * 1991-01-18 1992-08-25 Mitsubishi Electric Corp マイクロコンピュータシステム
US5333272A (en) * 1991-06-13 1994-07-26 International Business Machines Corporation Warning timer for users of interactive systems
JP3261665B2 (ja) * 1993-01-29 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション データ転送方法及びデータ処理システム
DE69507360T2 (de) * 1994-04-06 1999-06-17 Advanced Micro Devices, Inc., Sunnyvale, Calif. Parallelschlussschnittstellenschaltkreise in Rechnersystemen
US5754887A (en) * 1995-06-07 1998-05-19 International Business Machines Corporation System for limiting access of plurality of requests to peripheral bus by halting transmission to particular peripheral devices and resuming transmission after second predetermined time period expiration
US5574858A (en) * 1995-08-11 1996-11-12 Dell U.S.A., L.P. Method and apparatus for, upon receipt of data from a mouse, requiring the remainder of data needed to constitute a packet to be received within one second
US5802269A (en) * 1996-06-28 1998-09-01 Intel Corporation Method and apparatus for power management of distributed direct memory access (DDMA) devices
US6000043A (en) * 1996-06-28 1999-12-07 Intel Corporation Method and apparatus for management of peripheral devices coupled to a bus
US6584587B1 (en) * 1999-10-14 2003-06-24 Sony Corporation Watchdog method and apparatus
US6543003B1 (en) * 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor
US6496890B1 (en) 1999-12-03 2002-12-17 Michael Joseph Azevedo Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters
US6658510B1 (en) * 2000-10-18 2003-12-02 International Business Machines Corporation Software method to retry access to peripherals that can cause bus timeouts during momentary busy periods
US20070260777A1 (en) * 2003-11-25 2007-11-08 Timpe Barrie R Queues for information processing and methods thereof
TWI311705B (en) * 2005-05-23 2009-07-01 Via Tech Inc Peripheral component interconnect express and changing method of link power states thereof
US20090113143A1 (en) * 2007-10-26 2009-04-30 Dell Products L.P. Systems and methods for managing local and remote memory access
CN106325739A (zh) * 2016-08-01 2017-01-11 孟海同 经过点阵轨迹的表现和在软件中输入轨迹打开链接的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4475011A (en) * 1977-12-27 1984-10-02 Stromberg-Carlson Corporation Arrangement of interactive telephone switching processors providing selective functional capability by port
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
US4426679A (en) * 1980-09-29 1984-01-17 Honeywell Information Systems Inc. Communication multiplexer using a random access memory for storing an acknowledge response to an input/output command from a central processor
US4562533A (en) * 1981-12-03 1985-12-31 Ncr Corporation Data communications system to system adapter
US4733351A (en) * 1984-12-31 1988-03-22 Wang Laboratories, Inc. Terminal protocols
US4858108A (en) * 1985-03-20 1989-08-15 Hitachi, Ltd. Priority control architecture for input/output operation

Also Published As

Publication number Publication date
EP0306043B1 (de) 1994-05-11
US4872110A (en) 1989-10-03
AU2171088A (en) 1989-03-09
EP0306043A3 (en) 1990-06-13
DE3889511T2 (de) 1994-12-15
AU602238B2 (en) 1990-10-04
CA1308199C (en) 1992-09-29
EP0306043A2 (de) 1989-03-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL HN INFORMATION SYSTEMS INC., BILLERICA, MASS.

8339 Ceased/non-payment of the annual fee