DE3887851D1 - Makrozellenmuster für halbleiterintegrierten Schaltkreis. - Google Patents

Makrozellenmuster für halbleiterintegrierten Schaltkreis.

Info

Publication number
DE3887851D1
DE3887851D1 DE88120925T DE3887851T DE3887851D1 DE 3887851 D1 DE3887851 D1 DE 3887851D1 DE 88120925 T DE88120925 T DE 88120925T DE 3887851 T DE3887851 T DE 3887851T DE 3887851 D1 DE3887851 D1 DE 3887851D1
Authority
DE
Germany
Prior art keywords
integrated circuit
semiconductor integrated
macro cell
cell pattern
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88120925T
Other languages
English (en)
Other versions
DE3887851T2 (de
Inventor
Shigeru C O Patent Divi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3887851D1 publication Critical patent/DE3887851D1/de
Publication of DE3887851T2 publication Critical patent/DE3887851T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7896—Modular architectures, e.g. assembled from a number of identical packages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE3887851T 1987-12-16 1988-12-14 Makrozellenmuster für halbleiterintegrierten Schaltkreis. Expired - Fee Related DE3887851T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62317860A JPH01158758A (ja) 1987-12-16 1987-12-16 半導体集積回路

Publications (2)

Publication Number Publication Date
DE3887851D1 true DE3887851D1 (de) 1994-03-24
DE3887851T2 DE3887851T2 (de) 1994-05-19

Family

ID=18092867

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3887851T Expired - Fee Related DE3887851T2 (de) 1987-12-16 1988-12-14 Makrozellenmuster für halbleiterintegrierten Schaltkreis.

Country Status (5)

Country Link
US (1) US4972324A (de)
EP (1) EP0320919B1 (de)
JP (1) JPH01158758A (de)
KR (1) KR920000382B1 (de)
DE (1) DE3887851T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173864A (en) * 1988-08-20 1992-12-22 Kabushiki Kaisha Toshiba Standard cell and standard-cell-type integrated circuit
US5210701A (en) * 1989-05-15 1993-05-11 Cascade Design Automation Corporation Apparatus and method for designing integrated circuit modules
JPH04116951A (ja) * 1990-09-07 1992-04-17 Fujitsu Ltd 半導体集積回路
JP2575564B2 (ja) * 1991-03-05 1997-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 自動マクロ最適順序化方法
US5682323A (en) 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
US10132770B2 (en) * 2009-05-15 2018-11-20 A. O. Smith Corporation Flame rod analysis system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703436A (en) * 1984-02-01 1987-10-27 Inova Microelectronics Corporation Wafer level integration technique
JPH0652784B2 (ja) * 1984-12-07 1994-07-06 富士通株式会社 ゲートアレイ集積回路装置及びその製造方法
US4641247A (en) * 1985-08-30 1987-02-03 Advanced Micro Devices, Inc. Bit-sliced, dual-bus design of integrated circuits

Also Published As

Publication number Publication date
JPH01158758A (ja) 1989-06-21
DE3887851T2 (de) 1994-05-19
KR920000382B1 (ko) 1992-01-13
EP0320919B1 (de) 1994-02-16
JPH055379B2 (de) 1993-01-22
KR890011078A (ko) 1989-08-12
US4972324A (en) 1990-11-20
EP0320919A2 (de) 1989-06-21
EP0320919A3 (en) 1990-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee