DE3881222D1 - SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS THROUGH TWO SEPARATE INPUTS / OUTPUTS. - Google Patents

SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS THROUGH TWO SEPARATE INPUTS / OUTPUTS.

Info

Publication number
DE3881222D1
DE3881222D1 DE8888100197T DE3881222T DE3881222D1 DE 3881222 D1 DE3881222 D1 DE 3881222D1 DE 8888100197 T DE8888100197 T DE 8888100197T DE 3881222 T DE3881222 T DE 3881222T DE 3881222 D1 DE3881222 D1 DE 3881222D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
outputs
operated
output
data input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888100197T
Other languages
German (de)
Inventor
Hans Juergen Dr Rer Mattausch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE8888100197T priority Critical patent/DE3881222D1/en
Application granted granted Critical
Publication of DE3881222D1 publication Critical patent/DE3881222D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The dual port random access semiconductor memory has a separate address control (8,10;9,11) and a separate read/write path (12,13) for each data input/ output (DEA1,DEA2) and a clock circuit (20) allowing the address controls (8,10;9,11) and the bias circuits (16,17) for the data lines (L1,L1';L2,L2') associated with the read/ write paths (12,13) to be operated in alternation. During one clock phase the address control (8,10) of the first data input/output (DEA1) and the bias circuit (17) for the other data lines (L2,L2') are operated and during the second clock phase the address control (9,11) for the second data input/output (DEA2) and the bias circuit (16) for the first data lines (L1,L1') are operated.
DE8888100197T 1987-01-23 1988-01-08 SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS THROUGH TWO SEPARATE INPUTS / OUTPUTS. Expired - Fee Related DE3881222D1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE8888100197T DE3881222D1 (en) 1987-01-23 1988-01-08 SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS THROUGH TWO SEPARATE INPUTS / OUTPUTS.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3701976 1987-01-23
DE8888100197T DE3881222D1 (en) 1987-01-23 1988-01-08 SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS THROUGH TWO SEPARATE INPUTS / OUTPUTS.

Publications (1)

Publication Number Publication Date
DE3881222D1 true DE3881222D1 (en) 1993-07-01

Family

ID=6319407

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888100197T Expired - Fee Related DE3881222D1 (en) 1987-01-23 1988-01-08 SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS THROUGH TWO SEPARATE INPUTS / OUTPUTS.

Country Status (5)

Country Link
US (1) US4860263A (en)
EP (1) EP0275884B1 (en)
JP (1) JPS63188887A (en)
AT (1) ATE89946T1 (en)
DE (1) DE3881222D1 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3835116A1 (en) * 1988-10-14 1990-04-19 Siemens Ag ADDRESS AMPLIFIER CIRCUIT WITH SELF-LOCKING AND SECURING AGAINST MULTIPLE ADDRESSING FOR USE IN STATIC GAAS RAMS
US4975872A (en) * 1988-11-17 1990-12-04 Matsushita Electric Industrial Co., Ltd. Dual port memory device with tag bit marking
FR2639461A1 (en) * 1988-11-18 1990-05-25 Labo Electronique Physique BIDIMENSIONAL ARRANGEMENT OF MEMORY POINTS AND STRUCTURE OF NEURON NETWORKS USING SUCH ARRANGEMENT
US5014247A (en) * 1988-12-19 1991-05-07 Advanced Micro Devices, Inc. System for accessing the same memory location by two different devices
JPH02177195A (en) * 1988-12-28 1990-07-10 Fujitsu Ltd Two-port static ram
US5210701A (en) * 1989-05-15 1993-05-11 Cascade Design Automation Corporation Apparatus and method for designing integrated circuit modules
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
JPH03224197A (en) * 1990-01-30 1991-10-03 Toshiba Corp Multiport ram and information processor
US5003509A (en) * 1990-03-27 1991-03-26 National Semiconductor Corp. Multi-port, bipolar-CMOS memory cell
JP2965043B2 (en) * 1990-04-10 1999-10-18 三菱電機株式会社 Dual port memory
US5465344A (en) * 1990-08-20 1995-11-07 Matsushita Electric Industrial Co., Ltd. Microprocessor with dual-port cache memory for reducing penalty of consecutive memory address accesses
JP2673390B2 (en) * 1991-03-13 1997-11-05 三菱電機株式会社 Multi-port memory
US5371877A (en) * 1991-12-31 1994-12-06 Apple Computer, Inc. Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory
US5504503A (en) * 1993-12-03 1996-04-02 Lsi Logic Corporation High speed signal conversion method and device
US5581720A (en) * 1994-04-15 1996-12-03 David Sarnoff Research Center, Inc. Apparatus and method for updating information in a microcode instruction

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165983A (en) * 1980-05-26 1981-12-19 Toshiba Corp Semiconductor storage device
US4395765A (en) * 1981-04-23 1983-07-26 Bell Telephone Laboratories, Incorporated Multiport memory array
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
JPS59198584A (en) * 1983-04-22 1984-11-10 Nec Corp Multiaccess storage device
US4520465A (en) * 1983-05-05 1985-05-28 Motorola, Inc. Method and apparatus for selectively precharging column lines of a memory
JPS6072020A (en) * 1983-09-29 1985-04-24 Nec Corp Dual port memory circuit
JPS60140924A (en) * 1983-12-27 1985-07-25 Nec Corp Semiconductor circuit
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array

Also Published As

Publication number Publication date
EP0275884A2 (en) 1988-07-27
US4860263A (en) 1989-08-22
EP0275884B1 (en) 1993-05-26
EP0275884A3 (en) 1990-12-05
ATE89946T1 (en) 1993-06-15
JPS63188887A (en) 1988-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee