DE3879321D1 - Bestimmung des aetzungsendpunktes. - Google Patents

Bestimmung des aetzungsendpunktes.

Info

Publication number
DE3879321D1
DE3879321D1 DE8888113027T DE3879321T DE3879321D1 DE 3879321 D1 DE3879321 D1 DE 3879321D1 DE 8888113027 T DE8888113027 T DE 8888113027T DE 3879321 T DE3879321 T DE 3879321T DE 3879321 D1 DE3879321 D1 DE 3879321D1
Authority
DE
Germany
Prior art keywords
determination
end point
action end
action
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888113027T
Other languages
English (en)
Other versions
DE3879321T2 (de
Inventor
Paul E Riley
Vivek D Kulkarni
Egil D Castel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE3879321D1 publication Critical patent/DE3879321D1/de
Application granted granted Critical
Publication of DE3879321T2 publication Critical patent/DE3879321T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/013—Devices or means for detecting lapping completion
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19883879321 1987-08-14 1988-08-11 Bestimmung des aetzungsendpunktes. Expired - Fee Related DE3879321T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8599887A 1987-08-14 1987-08-14

Publications (2)

Publication Number Publication Date
DE3879321D1 true DE3879321D1 (de) 1993-04-22
DE3879321T2 DE3879321T2 (de) 1993-09-16

Family

ID=22195307

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883879321 Expired - Fee Related DE3879321T2 (de) 1987-08-14 1988-08-11 Bestimmung des aetzungsendpunktes.

Country Status (4)

Country Link
EP (1) EP0304729B1 (de)
JP (1) JPH01295423A (de)
CA (1) CA1286801C (de)
DE (1) DE3879321T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0490236A3 (en) * 1990-12-13 1992-08-12 National Semiconductor Corporation Fabrication process for schottky barrier diodes on a substrate
EP0543449B1 (de) * 1991-11-19 1997-03-05 Koninklijke Philips Electronics N.V. Herstellungsverfahren für eine Halbleitervorrichtung mit durch eine Aluminiumverbindung seitlich voneinander isolierten Aluminiumspuren
JP2611615B2 (ja) * 1992-12-15 1997-05-21 日本電気株式会社 半導体装置の製造方法
US5955380A (en) * 1997-09-30 1999-09-21 Siemens Aktiengesellschaft Endpoint detection method and apparatus
US6489612B1 (en) * 1999-04-21 2002-12-03 Seiko Instruments Inc. Method of measuring film thickness
JP4497302B2 (ja) * 2004-09-22 2010-07-07 リコー光学株式会社 エッチバック方法、及びそれを用いた無機偏光子製造方法
DE102006035668B4 (de) * 2006-07-31 2014-02-20 Globalfoundries Inc. Verfahren zum Herstellen einer Ätzindikator- und Ätzstoppschicht zur Reduzierung von Ätzungleichförmigkeiten
TWI624890B (zh) 2013-08-22 2018-05-21 Sakura Color Prod Corp Indicator for electronic component manufacturing apparatus, and design and/or management method of the same
CN106030766B (zh) 2014-02-14 2019-05-28 株式会社樱花彩色笔 等离子体处理检测指示器
JP2015205995A (ja) 2014-04-21 2015-11-19 株式会社サクラクレパス プラズマ処理検知用インキ組成物及びプラズマ処理検知インジケータ
WO2015170592A1 (ja) * 2014-05-09 2015-11-12 株式会社サクラクレパス 変色層として無機物質を使用したプラズマ処理検知インジケータ
JP6567863B2 (ja) 2014-09-16 2019-08-28 株式会社サクラクレパス プラズマ処理検知用インキ組成物及びプラズマ処理検知インジケータ
JP6567817B2 (ja) 2014-12-02 2019-08-28 株式会社サクラクレパス プラズマ処理検知インキ組成物及びそれを用いたプラズマ処理検知インジケータ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6039175A (ja) * 1983-08-10 1985-02-28 Hitachi Ltd ドライエツチング方法
JPS6092634A (ja) * 1983-10-26 1985-05-24 Nec Corp 半導体装置の製造方法
JPS61260677A (ja) * 1985-05-15 1986-11-18 Mitsubishi Electric Corp 半導体装置の製造方法
JPS61107743A (ja) * 1984-10-30 1986-05-26 Nec Corp 半導体装置の製造方法
JPS61285720A (ja) * 1985-06-12 1986-12-16 Fujitsu Ltd 半導体装置の製造方法
FR2587838B1 (fr) * 1985-09-20 1987-11-27 Radiotechnique Compelec Procede pour aplanir la surface d'un dispositif semi-conducteur utilisant du nitrure de silicium comme materiau isolant
JPS6273723A (ja) * 1985-09-27 1987-04-04 Sumitomo Electric Ind Ltd エツチバツク法による平坦化工程終点検出方法

Also Published As

Publication number Publication date
EP0304729B1 (de) 1993-03-17
CA1286801C (en) 1991-07-23
JPH01295423A (ja) 1989-11-29
EP0304729A1 (de) 1989-03-01
DE3879321T2 (de) 1993-09-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee