DE3867837D1 - Eingangs-/ausgangsarchitektur fuer ringverbundene verteilte-speicher-parallelrechner. - Google Patents

Eingangs-/ausgangsarchitektur fuer ringverbundene verteilte-speicher-parallelrechner.

Info

Publication number
DE3867837D1
DE3867837D1 DE8888909424T DE3867837T DE3867837D1 DE 3867837 D1 DE3867837 D1 DE 3867837D1 DE 8888909424 T DE8888909424 T DE 8888909424T DE 3867837 T DE3867837 T DE 3867837T DE 3867837 D1 DE3867837 D1 DE 3867837D1
Authority
DE
Germany
Prior art keywords
ring
input
distributed storage
parallel computers
output architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888909424T
Other languages
English (en)
Inventor
Steven Cok
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Application granted granted Critical
Publication of DE3867837D1 publication Critical patent/DE3867837D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
DE8888909424T 1987-10-08 1988-09-29 Eingangs-/ausgangsarchitektur fuer ringverbundene verteilte-speicher-parallelrechner. Expired - Fee Related DE3867837D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/105,836 US4942517A (en) 1987-10-08 1987-10-08 Enhanced input/output architecture for toroidally-connected distributed-memory parallel computers
PCT/US1988/003340 WO1989003564A1 (en) 1987-10-08 1988-09-29 Enhanced input/ouput architecture for toroidally-connected distributed-memory parallel computers

Publications (1)

Publication Number Publication Date
DE3867837D1 true DE3867837D1 (de) 1992-02-27

Family

ID=22308046

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888909424T Expired - Fee Related DE3867837D1 (de) 1987-10-08 1988-09-29 Eingangs-/ausgangsarchitektur fuer ringverbundene verteilte-speicher-parallelrechner.

Country Status (5)

Country Link
US (1) US4942517A (de)
EP (1) EP0334943B1 (de)
JP (1) JPH03500585A (de)
DE (1) DE3867837D1 (de)
WO (1) WO1989003564A1 (de)

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JP2642039B2 (ja) * 1992-05-22 1997-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション アレイ・プロセッサ
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Also Published As

Publication number Publication date
JPH03500585A (ja) 1991-02-07
US4942517A (en) 1990-07-17
EP0334943A1 (de) 1989-10-04
WO1989003564A1 (en) 1989-04-20
EP0334943B1 (de) 1992-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee