DE3864232D1 - Anordnung zur strukturellen pruefung einer integrierten schaltung. - Google Patents

Anordnung zur strukturellen pruefung einer integrierten schaltung.

Info

Publication number
DE3864232D1
DE3864232D1 DE8888402521T DE3864232T DE3864232D1 DE 3864232 D1 DE3864232 D1 DE 3864232D1 DE 8888402521 T DE8888402521 T DE 8888402521T DE 3864232 T DE3864232 T DE 3864232T DE 3864232 D1 DE3864232 D1 DE 3864232D1
Authority
DE
Germany
Prior art keywords
arrangement
integrated circuit
structural testing
testing
structural
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888402521T
Other languages
English (en)
Inventor
Jacek Kowalski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE3864232D1 publication Critical patent/DE3864232D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
DE8888402521T 1987-10-19 1988-10-05 Anordnung zur strukturellen pruefung einer integrierten schaltung. Expired - Fee Related DE3864232D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8714344A FR2622019B1 (fr) 1987-10-19 1987-10-19 Dispositif de test structurel d'un circuit integre

Publications (1)

Publication Number Publication Date
DE3864232D1 true DE3864232D1 (de) 1991-09-19

Family

ID=9355909

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888402521T Expired - Fee Related DE3864232D1 (de) 1987-10-19 1988-10-05 Anordnung zur strukturellen pruefung einer integrierten schaltung.

Country Status (6)

Country Link
US (1) US5060198A (de)
EP (1) EP0313430B1 (de)
JP (1) JPH01147385A (de)
KR (1) KR890007084A (de)
DE (1) DE3864232D1 (de)
FR (1) FR2622019B1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69024086T2 (de) * 1989-04-13 1996-06-20 Sundisk Corp EEprom-System mit Blocklöschung
JP2745669B2 (ja) * 1989-04-27 1998-04-28 ブラザー工業株式会社 プリンタ
FR2656939B1 (fr) * 1990-01-09 1992-04-03 Sgs Thomson Microelectronics Verrous de securite pour circuit integre.
JPH0682325B2 (ja) * 1990-05-29 1994-10-19 株式会社東芝 情報処理装置のテスト容易化回路
EP0459001B1 (de) * 1990-05-31 1996-01-24 Siemens Aktiengesellschaft Integrierter Halbleiterspeicher
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device
KR920006993A (ko) * 1990-09-28 1992-04-28 정몽헌 Epld의 입출력 마크로셀 시험회로
JP2619170B2 (ja) * 1990-10-02 1997-06-11 株式会社東芝 半導体メモリ及びその試験方法
WO1992019052A1 (en) * 1991-04-19 1992-10-29 Vlsi Technology, Inc. Mappable test structure for gate array circuit and method for testing the same
FR2690008B1 (fr) * 1991-05-29 1994-06-10 Gemplus Card Int Memoire avec cellule memoire eeprom a effet capacitif et procede de lecture d'une telle cellule memoire.
FR2683342B1 (fr) * 1991-10-31 1994-01-07 Gemplus Card International Circuit d'interface pour carte a circuit integre.
US5235549A (en) * 1991-12-23 1993-08-10 Intel Corporation Semiconductor device with apparatus for performing electrical tests on single memory cells
FR2686989B1 (fr) * 1992-01-30 1997-01-17 Gemplus Card Int Procede de comptage de securite pour un compteur electronique binaire.
JPH06215599A (ja) * 1993-01-13 1994-08-05 Nec Corp 半導体記憶回路
FR2703501B1 (fr) * 1993-04-01 1995-05-19 Gemplus Card Int Circuit intégré pour carte à mémoire et procédé de décomptage d'unités dans une carte à mémoire.
FR2703526B1 (fr) * 1993-04-02 1995-05-19 Gemplus Card Int Circuit de déclenchement automatique.
FR2705810B1 (fr) * 1993-05-26 1995-06-30 Gemplus Card Int Puce de carte à puce munie d'un moyen de limitation du nombre d'authentifications.
US5440516A (en) * 1994-01-27 1995-08-08 Sgs-Thomson Microelectronics, Inc. Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
DE4413257A1 (de) * 1994-04-16 1995-10-19 Philips Patentverwaltung Integrierte Schaltungsanordnung mit einem EEPROM, Halbleiterscheibe mit solchen integrierten Schaltungen sowie Verfahren zur Verwendung einer solchen Halbleiterscheibe
US5633828A (en) * 1995-08-24 1997-05-27 Sgs-Thomson Microelectronics, Inc. Circuitry and methodology to test single bit failures of integrated circuit memory devices
FR2739737B1 (fr) * 1995-10-09 1997-11-21 Inside Technologies Perfectionnements aux cartes a memoire
FR2739706B1 (fr) * 1995-10-09 1997-11-21 Inside Technologies Perfectionnements aux cartes a memoire
KR100230427B1 (ko) * 1997-06-23 1999-11-15 윤종용 박막 트랜지스터용 액정표시장치 소스드라이버에서의 디코더 테스트방법 및 이를 이용한 디코더 테스트 제어장치
JP3204450B2 (ja) * 1998-04-15 2001-09-04 日本電気株式会社 アドレスデコード回路及びアドレスデコード方法
US9196381B2 (en) * 2012-11-01 2015-11-24 Futurewei Technologies, Inc. Technique to operate memory in functional mode under LBIST test

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481627A (en) * 1981-10-30 1984-11-06 Honeywell Information Systems Inc. Embedded memory testing method and apparatus
DE3232215A1 (de) * 1982-08-30 1984-03-01 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierte digitale halbleiterschaltung
ATE53261T1 (de) * 1985-03-26 1990-06-15 Siemens Ag Verfahren zum betreiben eines halbleiterspeichers mit integrierter paralleltestmoeglichkeit und auswerteschaltung zur durchfuehrung des verfahrens.
JPS61289600A (ja) * 1985-06-17 1986-12-19 Fujitsu Ltd 半導体記憶装置
JPS62136680U (de) * 1986-02-21 1987-08-28
US4829520A (en) * 1987-03-16 1989-05-09 American Telephone And Telegraph Company, At&T Bell Laboratories In-place diagnosable electronic circuit board

Also Published As

Publication number Publication date
FR2622019B1 (fr) 1990-02-09
KR890007084A (ko) 1989-06-17
JPH01147385A (ja) 1989-06-09
FR2622019A1 (fr) 1989-04-21
EP0313430A1 (de) 1989-04-26
US5060198A (en) 1991-10-22
EP0313430B1 (de) 1991-08-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee