DE3855683D1 - Daten-Transferschaltung - Google Patents

Daten-Transferschaltung

Info

Publication number
DE3855683D1
DE3855683D1 DE3855683T DE3855683T DE3855683D1 DE 3855683 D1 DE3855683 D1 DE 3855683D1 DE 3855683 T DE3855683 T DE 3855683T DE 3855683 T DE3855683 T DE 3855683T DE 3855683 D1 DE3855683 D1 DE 3855683D1
Authority
DE
Germany
Prior art keywords
data transfer
transfer circuit
circuit
data
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855683T
Other languages
English (en)
Other versions
DE3855683T2 (de
Inventor
Yuji C O Patent Divis Watanabe
Haruki C O Patent Divisio Toda
Hiroshi C O Patent Divi Sahara
Shigeo C O Patent Divi Ohshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3855683D1 publication Critical patent/DE3855683D1/de
Application granted granted Critical
Publication of DE3855683T2 publication Critical patent/DE3855683T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Communication Control (AREA)
DE3855683T 1987-12-26 1988-12-23 Daten-Transferschaltung Expired - Fee Related DE3855683T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62330500A JP2501344B2 (ja) 1987-12-26 1987-12-26 デ―タ転送回路

Publications (2)

Publication Number Publication Date
DE3855683D1 true DE3855683D1 (de) 1997-01-09
DE3855683T2 DE3855683T2 (de) 1997-05-07

Family

ID=18233317

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855683T Expired - Fee Related DE3855683T2 (de) 1987-12-26 1988-12-23 Daten-Transferschaltung

Country Status (6)

Country Link
US (1) US4995003A (de)
EP (1) EP0322784B1 (de)
JP (1) JP2501344B2 (de)
KR (1) KR910007642B1 (de)
DE (1) DE3855683T2 (de)
MY (1) MY103949A (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2880547B2 (ja) * 1990-01-19 1999-04-12 三菱電機株式会社 半導体記憶装置
DE69130554T2 (de) * 1990-09-07 1999-08-12 Nec Corp., Tokio/Tokyo Registerschaltung zum Kopieren des Inhalts eines Registers in ein anderes Register
FR2667688B1 (fr) * 1990-10-05 1994-04-29 Commissariat Energie Atomique Circuit d'acquisition ultrarapide.
JP2604276B2 (ja) * 1990-11-20 1997-04-30 三菱電機株式会社 半導体記憶装置
US6028796A (en) * 1992-04-02 2000-02-22 Sony Corporation Read-out circuit for semiconductor memory device
JP3372970B2 (ja) * 1992-09-02 2003-02-04 シャープ株式会社 自己同期型転送制御回路
US5373470A (en) * 1993-03-26 1994-12-13 United Memories, Inc. Method and circuit for configuring I/O devices
JP3253547B2 (ja) * 1996-03-28 2002-02-04 株式会社沖データ データ転送システム
US7349266B2 (en) * 2004-06-10 2008-03-25 Freescale Semiconductor, Inc. Memory device with a data hold latch

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618033A (en) * 1968-12-26 1971-11-02 Bell Telephone Labor Inc Transistor shift register using bidirectional gates connected between register stages
US3781821A (en) * 1972-06-02 1973-12-25 Ibm Selective shift register
JPS58182185A (ja) * 1982-04-19 1983-10-25 Nec Corp 半導体記憶装置
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM
US4764901A (en) * 1984-08-03 1988-08-16 Kabushiki Kaisha Toshiba Semiconductor memory device capable of being accessed before completion of data output
US4745577A (en) * 1984-11-20 1988-05-17 Fujitsu Limited Semiconductor memory device with shift registers for high speed reading and writing
US4685088A (en) * 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques
JPS61271690A (ja) * 1985-05-27 1986-12-01 Matsushita Electric Ind Co Ltd 半導体メモリの読み出し回路
JPS62143279A (ja) * 1985-12-18 1987-06-26 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JPH01173388A (ja) 1989-07-10
KR910007642B1 (ko) 1991-09-28
JP2501344B2 (ja) 1996-05-29
EP0322784A2 (de) 1989-07-05
DE3855683T2 (de) 1997-05-07
MY103949A (en) 1993-10-30
EP0322784A3 (de) 1990-10-31
KR890010728A (ko) 1989-08-10
EP0322784B1 (de) 1996-11-27
US4995003A (en) 1991-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee