DE3854320D1 - Logikredundanzschaltungsaufstellung. - Google Patents

Logikredundanzschaltungsaufstellung.

Info

Publication number
DE3854320D1
DE3854320D1 DE3854320T DE3854320T DE3854320D1 DE 3854320 D1 DE3854320 D1 DE 3854320D1 DE 3854320 T DE3854320 T DE 3854320T DE 3854320 T DE3854320 T DE 3854320T DE 3854320 D1 DE3854320 D1 DE 3854320D1
Authority
DE
Germany
Prior art keywords
redundancy circuitry
logic redundancy
logic
circuitry
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3854320T
Other languages
English (en)
Other versions
DE3854320T2 (de
Inventor
James Joseph Curtin
Jack Arthur Dorler
George John Jordy
Kenneth Louis Leiner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3854320D1 publication Critical patent/DE3854320D1/de
Publication of DE3854320T2 publication Critical patent/DE3854320T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2051—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant in regular structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Safety Devices In Control Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
DE3854320T 1987-11-13 1988-09-27 Logikredundanzschaltungsaufstellung. Expired - Fee Related DE3854320T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/120,431 US4798976A (en) 1987-11-13 1987-11-13 Logic redundancy circuit scheme

Publications (2)

Publication Number Publication Date
DE3854320D1 true DE3854320D1 (de) 1995-09-21
DE3854320T2 DE3854320T2 (de) 1996-04-18

Family

ID=22390229

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3854320T Expired - Fee Related DE3854320T2 (de) 1987-11-13 1988-09-27 Logikredundanzschaltungsaufstellung.

Country Status (4)

Country Link
US (1) US4798976A (de)
EP (1) EP0317472B1 (de)
JP (1) JPH0736517B2 (de)
DE (1) DE3854320T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9222840D0 (en) * 1992-10-31 1992-12-16 Smiths Industries Plc Electronic assemblies
US5434514A (en) * 1992-11-19 1995-07-18 Altera Corporation Programmable logic devices with spare circuits for replacement of defects
US5369314A (en) * 1994-02-22 1994-11-29 Altera Corporation Programmable logic device with redundant circuitry
CA2185787A1 (en) * 1994-03-22 1995-09-28 Richard S. Norman Efficient direct cell replacement fault tolerant architecture supporting completely integrated systems with means for direct communication with system operator
US6408402B1 (en) 1994-03-22 2002-06-18 Hyperchip Inc. Efficient direct replacement cell fault tolerant architecture
US5592102A (en) * 1995-10-19 1997-01-07 Altera Corporation Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
US6034536A (en) * 1997-02-05 2000-03-07 Altera Corporation Redundancy circuitry for logic circuits
US6091258A (en) * 1997-02-05 2000-07-18 Altera Corporation Redundancy circuitry for logic circuits
DE69802927T2 (de) * 1997-05-23 2002-08-08 Altera Corp A Delaware Corp Sa Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen
US6201404B1 (en) 1998-07-14 2001-03-13 Altera Corporation Programmable logic device with redundant circuitry
US7702975B2 (en) * 2008-04-08 2010-04-20 International Business Machines Corporation Integration of LBIST into array BISR flow
US9274171B1 (en) 2014-11-12 2016-03-01 International Business Machines Corporation Customer-transparent logic redundancy for improved yield

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1186704A (en) * 1968-03-01 1970-04-02 Ibm Selection Circuit
US3665418A (en) * 1968-07-15 1972-05-23 Ibm Status switching in an automatically repaired computer
US3665173A (en) * 1968-09-03 1972-05-23 Ibm Triple modular redundancy/sparing
US3800164A (en) * 1969-01-02 1974-03-26 Us Navy Redundant logic circuit
US3750173A (en) * 1970-07-29 1973-07-31 Us Navy Frequency translating repeater (boomerang) using single-sideband techniques
US3670148A (en) * 1970-09-14 1972-06-13 Lear Siegler Inc Selective signal transmission system
DE2059797B1 (de) * 1970-12-04 1972-05-25 Siemens Ag Taktversorgungsanlage
US3818243A (en) * 1971-09-09 1974-06-18 Massachusetts Inst Technology Error correction by redundant pulse powered circuits
US3805039A (en) * 1972-11-30 1974-04-16 Raytheon Co High reliability system employing subelement redundancy
US3859513A (en) * 1973-02-28 1975-01-07 Univ Washington Switching and digital system
CH623669A5 (de) * 1973-11-14 1981-06-15 Agie Ag Ind Elektronik
US4015246A (en) * 1975-04-14 1977-03-29 The Charles Stark Draper Laboratory, Inc. Synchronous fault tolerant multi-processor system
GB2089536B (en) * 1980-12-12 1984-05-23 Burroughs Corp Improvement in or relating to wafer scale integrated circuits
JPS59151400A (ja) * 1983-02-17 1984-08-29 Mitsubishi Electric Corp 半導体記憶装置
US4621201A (en) * 1984-03-30 1986-11-04 Trilogy Systems Corporation Integrated circuit redundancy and method for achieving high-yield production
JPS61163655A (ja) * 1985-01-14 1986-07-24 Toshiba Corp 相補型半導体集積回路
DE3514266A1 (de) * 1985-04-19 1986-10-23 Nixdorf Computer Ag, 4790 Paderborn Baustein zur erzeugung integrierter schaltungen
GB2177825B (en) * 1985-07-12 1989-07-26 Anamartic Ltd Control system for chained circuit modules
US4700187A (en) * 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array
US4709166A (en) * 1986-05-22 1987-11-24 International Business Machines Corporation Complementary cascoded logic circuit

Also Published As

Publication number Publication date
JPH01143415A (ja) 1989-06-06
EP0317472A3 (de) 1991-05-29
DE3854320T2 (de) 1996-04-18
JPH0736517B2 (ja) 1995-04-19
EP0317472B1 (de) 1995-08-16
EP0317472A2 (de) 1989-05-24
US4798976A (en) 1989-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee