DE3853985T2 - Datenverarbeitungsanlage, geeignet für Hochgeschwindigkeitsverarbeitung. - Google Patents

Datenverarbeitungsanlage, geeignet für Hochgeschwindigkeitsverarbeitung.

Info

Publication number
DE3853985T2
DE3853985T2 DE3853985T DE3853985T DE3853985T2 DE 3853985 T2 DE3853985 T2 DE 3853985T2 DE 3853985 T DE3853985 T DE 3853985T DE 3853985 T DE3853985 T DE 3853985T DE 3853985 T2 DE3853985 T2 DE 3853985T2
Authority
DE
Germany
Prior art keywords
data processing
processing system
speed
speed processing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853985T
Other languages
English (en)
Other versions
DE3853985D1 (de
Inventor
Susumu Narita
Makoto Hanawa
Tadahiko Nishimukai
Tetsuhiko Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3853985D1 publication Critical patent/DE3853985D1/de
Publication of DE3853985T2 publication Critical patent/DE3853985T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE3853985T 1987-12-25 1988-12-22 Datenverarbeitungsanlage, geeignet für Hochgeschwindigkeitsverarbeitung. Expired - Fee Related DE3853985T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32714287 1987-12-25

Publications (2)

Publication Number Publication Date
DE3853985D1 DE3853985D1 (de) 1995-07-20
DE3853985T2 true DE3853985T2 (de) 1996-02-22

Family

ID=18195785

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853985T Expired - Fee Related DE3853985T2 (de) 1987-12-25 1988-12-22 Datenverarbeitungsanlage, geeignet für Hochgeschwindigkeitsverarbeitung.

Country Status (4)

Country Link
US (1) US5148532A (de)
EP (1) EP0322769B1 (de)
KR (1) KR970005453B1 (de)
DE (1) DE3853985T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5454090A (en) * 1990-10-12 1995-09-26 Siemens Aktiengesellschaft Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units
JP2773471B2 (ja) * 1991-07-24 1998-07-09 日本電気株式会社 情報処理装置
US5377335A (en) * 1991-08-30 1994-12-27 Unisys Corporation Multiple alternate path pipelined microsequencer and method for controlling a computer
US5742839A (en) * 1992-01-30 1998-04-21 Fujitsu Limited Coprocessor for performing an arithmetic operation by automatically reading data from an external memory
US5941986A (en) * 1993-04-30 1999-08-24 Intel Corporation Micro-code sequencer with branch-taken and branch-not-taken micro-code vectors sharing common address to eliminate taken branch penalties
JPH07182170A (ja) * 1993-12-24 1995-07-21 Ricoh Co Ltd マイクロプロセッサ
JP3504355B2 (ja) * 1994-12-06 2004-03-08 松下電器産業株式会社 プロセッサ
US6041403A (en) * 1996-09-27 2000-03-21 Intel Corporation Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
US7162612B2 (en) * 2000-08-16 2007-01-09 Ip-First, Llc Mechanism in a microprocessor for executing native instructions directly from memory
US6917608B1 (en) 2000-12-22 2005-07-12 National Semiconductor Corporation Microsequencer microcode bank switched architecture
US6963554B1 (en) 2000-12-27 2005-11-08 National Semiconductor Corporation Microwire dynamic sequencer pipeline stall
US20050278505A1 (en) * 2004-05-19 2005-12-15 Lim Seow C Microprocessor architecture including zero impact predictive data pre-fetch mechanism for pipeline data memory
US7971042B2 (en) 2005-09-28 2011-06-28 Synopsys, Inc. Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline
US8099721B2 (en) 2008-06-17 2012-01-17 Microsoft Corporation Parsing of declarations in all branches of preprocessor conditionals

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003033A (en) * 1975-12-22 1977-01-11 Honeywell Information Systems, Inc. Architecture for a microprogrammed device controller
GB1527289A (en) * 1976-08-17 1978-10-04 Int Computers Ltd Data processing systems
US4179737A (en) * 1977-12-23 1979-12-18 Burroughs Corporation Means and methods for providing greater speed and flexibility of microinstruction sequencing
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4551798A (en) * 1982-11-03 1985-11-05 Burroughs Corporation Multiple control stores in a pipelined microcontroller for handling nester subroutines
EP0150177A1 (de) * 1983-07-11 1985-08-07 Prime Computer, Inc. Datenverarbeitungsvorrichtung
EP0190484A3 (de) * 1985-01-28 1988-09-21 Data General Corporation Digitalrechner mit erhöhter Geschwindigkeit und Verfahren zur Geschwindigkeitserhöhung

Also Published As

Publication number Publication date
EP0322769B1 (de) 1995-06-14
US5148532A (en) 1992-09-15
KR970005453B1 (ko) 1997-04-16
EP0322769A2 (de) 1989-07-05
KR890010693A (ko) 1989-08-10
EP0322769A3 (de) 1992-05-20
DE3853985D1 (de) 1995-07-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee