DE3884103D1 - Zentraleinheit für digitales datenverarbeitungssystem, mit schreibpufferverwaltungsmechnismus. - Google Patents

Zentraleinheit für digitales datenverarbeitungssystem, mit schreibpufferverwaltungsmechnismus.

Info

Publication number
DE3884103D1
DE3884103D1 DE88902040T DE3884103T DE3884103D1 DE 3884103 D1 DE3884103 D1 DE 3884103D1 DE 88902040 T DE88902040 T DE 88902040T DE 3884103 T DE3884103 T DE 3884103T DE 3884103 D1 DE3884103 D1 DE 3884103D1
Authority
DE
Germany
Prior art keywords
data processing
processing system
digital data
central unit
buffer management
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88902040T
Other languages
English (en)
Inventor
Paul Rubinfeld
G Uhler
Robert Supnik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE3884103D1 publication Critical patent/DE3884103D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793Remedial or corrective actions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/461Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE88902040T 1987-02-24 1988-02-08 Zentraleinheit für digitales datenverarbeitungssystem, mit schreibpufferverwaltungsmechnismus. Expired - Lifetime DE3884103D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/017,518 US4851991A (en) 1987-02-24 1987-02-24 Central processor unit for digital data processing system including write buffer management mechanism

Publications (1)

Publication Number Publication Date
DE3884103D1 true DE3884103D1 (de) 1993-10-21

Family

ID=21783038

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88902040T Expired - Lifetime DE3884103D1 (de) 1987-02-24 1988-02-08 Zentraleinheit für digitales datenverarbeitungssystem, mit schreibpufferverwaltungsmechnismus.

Country Status (6)

Country Link
US (1) US4851991A (de)
EP (1) EP0303661B1 (de)
JP (1) JPH01502939A (de)
CA (1) CA1300280C (de)
DE (1) DE3884103D1 (de)
WO (1) WO1988006760A2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965721A (en) * 1987-03-31 1990-10-23 Bull Hn Information Systems Inc. Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication
US5317717A (en) * 1987-07-01 1994-05-31 Digital Equipment Corp. Apparatus and method for main memory unit protection using access and fault logic signals
US5003459A (en) * 1988-04-01 1991-03-26 Digital Equipment Corporation Cache memory system
US4993030A (en) * 1988-04-22 1991-02-12 Amdahl Corporation File system for a plurality of storage classes
CA2000139A1 (en) * 1988-10-04 1990-04-04 Wyn Y. Nielsen Distributed multiple irrigation controller management system
US5109490A (en) * 1989-01-13 1992-04-28 International Business Machines Corporation Data transfer using bus address lines
CA1325288C (en) * 1989-02-03 1993-12-14 Ricky C. Hetherington Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
DE3923872A1 (de) * 1989-07-19 1991-01-24 Philips Patentverwaltung Schaltungsanordnung zum steuern des zugriffs auf einen speicher
JPH0666056B2 (ja) * 1989-10-12 1994-08-24 甲府日本電気株式会社 情報処理システム
DE69032498T2 (de) * 1989-10-23 1999-03-04 Mitsubishi Denki K.K., Tokio/Tokyo Zellenvermittlungseinrichtung
EP0440243A3 (en) * 1990-01-31 1993-12-15 Nec Corp Memory controller for sub-memory unit such as disk drives
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5732241A (en) * 1990-06-27 1998-03-24 Mos Electronics, Corp. Random access cache memory controller and system
EP0510429A3 (en) * 1991-04-24 1993-12-01 Ibm Millicode register management system
US5398235A (en) * 1991-11-15 1995-03-14 Mitsubishi Denki Kabushiki Kaisha Cell exchanging apparatus
JP2671699B2 (ja) * 1991-11-15 1997-10-29 三菱電機株式会社 セル交換装置
GB2277181B (en) * 1991-12-23 1995-12-13 Intel Corp Interleaved cache for multiple accesses per clock in a microprocessor
JP2755039B2 (ja) * 1992-05-12 1998-05-20 日本電気株式会社 レジスタ・アクセス制御方式
JP3451103B2 (ja) * 1992-11-27 2003-09-29 富士通株式会社 データ通信装置及び方法
DE69433229T2 (de) * 1993-02-15 2004-08-12 Mitsubishi Denki K.K. ATM-Schalter
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
EP1215577B1 (de) * 2000-08-21 2012-02-22 Texas Instruments Incorporated Auf ID Aufgaben basierende Fehlerverwaltung und -beseitigung
JP2002358232A (ja) * 2001-05-31 2002-12-13 Mitsubishi Electric Corp メモリアクセス装置
CN1659131A (zh) 2002-04-08 2005-08-24 葛兰素集团有限公司 2-((2-烷氧基)-苯基)-环戊-1-烯基)芳香碳-以及杂环羧酸及其衍生物
KR100438736B1 (ko) * 2002-10-04 2004-07-05 삼성전자주식회사 어드레스 라인을 이용해 데이터 쓰기를 수행하는 메모리제어 장치
US8250412B2 (en) * 2003-09-26 2012-08-21 Ati Technologies Ulc Method and apparatus for monitoring and resetting a co-processor
US7702955B2 (en) 2005-12-28 2010-04-20 De Almeida Adrian S Method and apparatus for detecting a fault condition and restoration thereafter using user context information
KR102576159B1 (ko) * 2016-10-25 2023-09-08 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3737861A (en) * 1970-04-01 1973-06-05 Honeywell Inc Input/output bus
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
US4543628A (en) * 1983-01-28 1985-09-24 Digital Equipment Corporation Bus for data processing system with fault cycle operation
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
US4703418A (en) * 1985-06-28 1987-10-27 Hewlett-Packard Company Method and apparatus for performing variable length data read transactions
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions

Also Published As

Publication number Publication date
JPH01502939A (ja) 1989-10-05
JPH0559455B2 (de) 1993-08-31
US4851991A (en) 1989-07-25
EP0303661A1 (de) 1989-02-22
CA1300280C (en) 1992-05-05
EP0303661B1 (de) 1993-09-15
WO1988006760A2 (en) 1988-09-07
WO1988006760A3 (en) 1988-09-22

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Legal Events

Date Code Title Description
8332 No legal effect for de