DE3852909D1 - Lineare Kette von Parallelprozessoren und Benutzungsverfahren davon. - Google Patents

Lineare Kette von Parallelprozessoren und Benutzungsverfahren davon.

Info

Publication number
DE3852909D1
DE3852909D1 DE3852909T DE3852909T DE3852909D1 DE 3852909 D1 DE3852909 D1 DE 3852909D1 DE 3852909 T DE3852909 T DE 3852909T DE 3852909 T DE3852909 T DE 3852909T DE 3852909 D1 DE3852909 D1 DE 3852909D1
Authority
DE
Germany
Prior art keywords
methods
linear chain
parallel processors
processors
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3852909T
Other languages
English (en)
Other versions
DE3852909T2 (de
Inventor
Stephen S Wilson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Intelligent Systems Inc
Original Assignee
Applied Intelligent Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Intelligent Systems Inc filed Critical Applied Intelligent Systems Inc
Publication of DE3852909D1 publication Critical patent/DE3852909D1/de
Application granted granted Critical
Publication of DE3852909T2 publication Critical patent/DE3852909T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
DE3852909T 1987-06-01 1988-05-20 Lineare Kette von Parallelprozessoren und Benutzungsverfahren davon. Expired - Fee Related DE3852909T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/057,128 US5129092A (en) 1987-06-01 1987-06-01 Linear chain of parallel processors and method of using same

Publications (2)

Publication Number Publication Date
DE3852909D1 true DE3852909D1 (de) 1995-03-16
DE3852909T2 DE3852909T2 (de) 1995-10-12

Family

ID=22008678

Family Applications (2)

Application Number Title Priority Date Filing Date
DE198888108175T Pending DE293700T1 (de) 1987-06-01 1988-05-20 Lineare kette von parallelprozessoren und benutzungsverfahren davon.
DE3852909T Expired - Fee Related DE3852909T2 (de) 1987-06-01 1988-05-20 Lineare Kette von Parallelprozessoren und Benutzungsverfahren davon.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE198888108175T Pending DE293700T1 (de) 1987-06-01 1988-05-20 Lineare kette von parallelprozessoren und benutzungsverfahren davon.

Country Status (4)

Country Link
US (1) US5129092A (de)
EP (1) EP0293700B1 (de)
JP (1) JP2756257B2 (de)
DE (2) DE293700T1 (de)

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US5287416A (en) * 1989-10-10 1994-02-15 Unisys Corporation Parallel pipelined image processor
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US5325500A (en) * 1990-12-14 1994-06-28 Xerox Corporation Parallel processing units on a substrate, each including a column of memory
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US5732164A (en) * 1991-05-23 1998-03-24 Fujitsu Limited Parallel video processor apparatus
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US5450604A (en) * 1992-12-18 1995-09-12 Xerox Corporation Data rotation using parallel to serial units that receive data from memory units and rotation buffer that provides rotated data to memory units
US5408670A (en) * 1992-12-18 1995-04-18 Xerox Corporation Performing arithmetic in parallel on composite operands with packed multi-bit components
US5428804A (en) * 1992-12-18 1995-06-27 Xerox Corporation Edge crossing circuitry for SIMD architecture
US5450603A (en) * 1992-12-18 1995-09-12 Xerox Corporation SIMD architecture with transfer register or value source circuitry connected to bus
US5651121A (en) * 1992-12-18 1997-07-22 Xerox Corporation Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand
US5375080A (en) * 1992-12-18 1994-12-20 Xerox Corporation Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component
US5655131A (en) * 1992-12-18 1997-08-05 Xerox Corporation SIMD architecture for connection to host processor's bus
US5526501A (en) * 1993-08-12 1996-06-11 Hughes Aircraft Company Variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same
US5434629A (en) * 1993-12-20 1995-07-18 Focus Automation Systems Inc. Real-time line scan processor
US5557734A (en) * 1994-06-17 1996-09-17 Applied Intelligent Systems, Inc. Cache burst architecture for parallel processing, such as for image processing
US5630161A (en) * 1995-04-24 1997-05-13 Martin Marietta Corp. Serial-parallel digital signal processor
US6188381B1 (en) * 1997-09-08 2001-02-13 Sarnoff Corporation Modular parallel-pipelined vision system for real-time video processing
US6208772B1 (en) 1997-10-17 2001-03-27 Acuity Imaging, Llc Data processing system for logically adjacent data samples such as image data in a machine vision system
FR2793088B1 (fr) * 1999-04-30 2001-06-22 St Microelectronics Sa Procede et dispositif de collecte des valeurs logiques de sortie d'une unite logique dans un circuit electronique
US6598146B1 (en) * 1999-06-15 2003-07-22 Koninklijke Philips Electronics N.V. Data-processing arrangement comprising a plurality of processing and memory circuits
EP1122688A1 (de) 2000-02-04 2001-08-08 Texas Instruments Incorporated Verfahren und Vorrichtung zur Datenverarbeitung
ATE404923T1 (de) * 2001-03-02 2008-08-15 Mtek Vision Co Ltd Eine anordnung, um in einem datenprozessor den zugriff zu steuern
DE60238041D1 (de) * 2001-03-13 2010-12-02 Ecchandes Inc Visuelle einrichtung, verriegelnder zähler und bildsensor
HUP0102356A2 (hu) * 2001-06-06 2003-02-28 Afca-System Kft. Eljárás és kapcsolási elrendezés előnyösen ciklikusan ismétlődő adatfeldolgozási feladatok párhuzamos üzemű végrehajtására, továbbá az eljárás végrehajtásához szükséges műveleti kódok előállítására és szimulálására szolgáló programrendszer
US7054897B2 (en) * 2001-10-03 2006-05-30 Dsp Group, Ltd. Transposable register file
US20100274988A1 (en) * 2002-02-04 2010-10-28 Mimar Tibet Flexible vector modes of operation for SIMD processor
DE10206830B4 (de) * 2002-02-18 2004-10-14 Systemonic Ag Verfahren und Anordnung zur Zusammenführung von Daten aus parallelen Datenpfaden
US7506135B1 (en) * 2002-06-03 2009-03-17 Mimar Tibet Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements
US7737994B1 (en) * 2003-09-26 2010-06-15 Oracle America, Inc. Large-kernel convolution using multiple industry-standard graphics accelerators
US7266255B1 (en) * 2003-09-26 2007-09-04 Sun Microsystems, Inc. Distributed multi-sample convolution
JP2006099232A (ja) * 2004-09-28 2006-04-13 Renesas Technology Corp 半導体信号処理装置
US20060156316A1 (en) * 2004-12-18 2006-07-13 Gray Area Technologies System and method for application specific array processing
US20060190517A1 (en) * 2005-02-02 2006-08-24 Guerrero Miguel A Techniques for transposition of a matrix arranged in a memory as multiple items per word
US7783861B2 (en) * 2006-03-03 2010-08-24 Nec Corporation Data reallocation among PEs connected in both directions to respective PEs in adjacent blocks by selecting from inter-block and intra block transfers
GB2436377B (en) * 2006-03-23 2011-02-23 Cambridge Display Tech Ltd Data processing hardware
KR100834412B1 (ko) * 2007-05-23 2008-06-04 한국전자통신연구원 모바일 멀티미디어 연산의 효율적인 처리를 위한 병렬 프로세서
GB0809192D0 (en) * 2008-05-20 2008-06-25 Aspex Semiconductor Ltd Improvements to data compression engines
JP5601817B2 (ja) * 2009-10-28 2014-10-08 三菱電機株式会社 並列演算処理装置
JP5528976B2 (ja) * 2010-09-30 2014-06-25 株式会社メガチップス 画像処理装置
JP2011192305A (ja) * 2011-06-01 2011-09-29 Renesas Electronics Corp 半導体信号処理装置
US9183614B2 (en) 2011-09-03 2015-11-10 Mireplica Technology, Llc Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets
US9680916B2 (en) 2013-08-01 2017-06-13 Flowtraq, Inc. Methods and systems for distribution and retrieval of network traffic records
FR3015068B1 (fr) * 2013-12-18 2016-01-01 Commissariat Energie Atomique Module de traitement du signal, notamment pour reseau de neurones et circuit neuronal
EP3326115A1 (de) 2015-07-23 2018-05-30 Mireplica Technology, LLC Leistungsverbesserung für zweidimensionalen array-prozessor
US11249767B2 (en) * 2019-02-05 2022-02-15 Dell Products L.P. Boot assist zero overhead flash extended file system
US11042372B2 (en) * 2019-05-24 2021-06-22 Texas Instruments Incorporated Vector bit transpose

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US3537074A (en) * 1967-12-20 1970-10-27 Burroughs Corp Parallel operating array computer
US3582899A (en) * 1968-03-21 1971-06-01 Burroughs Corp Method and apparatus for routing data among processing elements of an array computer
US3970993A (en) * 1974-01-02 1976-07-20 Hughes Aircraft Company Cooperative-word linear array parallel processor
US4174514A (en) * 1976-11-15 1979-11-13 Environmental Research Institute Of Michigan Parallel partitioned serial neighborhood processors
EP0006748B1 (de) * 1978-06-26 1982-06-23 Environmental Research Institute Of Michigan Vorrichtung und Verfahren zur Erzeugung einer Transformation einer ersten Datenmatrix zur Bildung einer zweiten Datenmatrix
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US4314349A (en) * 1979-12-31 1982-02-02 Goodyear Aerospace Corporation Processing element for parallel array processors
US4525797A (en) * 1983-01-03 1985-06-25 Motorola, Inc. N-bit carry select adder circuit having only one full adder per bit
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4621339A (en) * 1983-06-13 1986-11-04 Duke University SIMD machine using cube connected cycles network architecture for vector processing
JPH0658631B2 (ja) * 1983-12-19 1994-08-03 株式会社日立製作所 デ−タ処理装置
FR2573888B1 (fr) * 1984-11-23 1987-01-16 Sintra Systeme pour la transmission simultanee de blocs de donnees ou de vecteurs entre une memoire et une ou plusieurs unites de traitement de donnees
US4787057A (en) * 1986-06-04 1988-11-22 General Electric Company Finite element analysis method using multiprocessor for matrix manipulations with special handling of diagonal elements
US4829585A (en) * 1987-05-04 1989-05-09 Polaroid Corporation Electronic image processing circuit

Also Published As

Publication number Publication date
US5129092A (en) 1992-07-07
EP0293700B1 (de) 1995-02-01
JP2756257B2 (ja) 1998-05-25
DE3852909T2 (de) 1995-10-12
EP0293700A3 (en) 1989-10-18
EP0293700A2 (de) 1988-12-07
DE293700T1 (de) 1990-04-12
JPS63316167A (ja) 1988-12-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee