DE3852862T2 - System zur umfassenden Ereignisqualifikation. - Google Patents
System zur umfassenden Ereignisqualifikation.Info
- Publication number
- DE3852862T2 DE3852862T2 DE3852862T DE3852862T DE3852862T2 DE 3852862 T2 DE3852862 T2 DE 3852862T2 DE 3852862 T DE3852862 T DE 3852862T DE 3852862 T DE3852862 T DE 3852862T DE 3852862 T2 DE3852862 T2 DE 3852862T2
- Authority
- DE
- Germany
- Prior art keywords
- event qualification
- comprehensive event
- comprehensive
- qualification
- event
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/117,114 US4857835A (en) | 1987-11-05 | 1987-11-05 | Global event qualification system |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3852862D1 DE3852862D1 (de) | 1995-03-09 |
DE3852862T2 true DE3852862T2 (de) | 1995-05-18 |
Family
ID=22371054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3852862T Expired - Fee Related DE3852862T2 (de) | 1987-11-05 | 1988-11-04 | System zur umfassenden Ereignisqualifikation. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4857835A (de) |
EP (1) | EP0315475B1 (de) |
JP (1) | JP2873233B2 (de) |
KR (1) | KR970005390B1 (de) |
DE (1) | DE3852862T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5329471A (en) * | 1987-06-02 | 1994-07-12 | Texas Instruments Incorporated | Emulation devices, systems and methods utilizing state machines |
US6522985B1 (en) | 1989-07-31 | 2003-02-18 | Texas Instruments Incorporated | Emulation devices, systems and methods utilizing state machines |
US6085336A (en) * | 1987-06-02 | 2000-07-04 | Texas Instruments Incorporated | Data processing devices, systems and methods with mode driven stops |
US5684721A (en) * | 1987-09-04 | 1997-11-04 | Texas Instruments Incorporated | Electronic systems and emulation and testing devices, cables, systems and methods |
US4857835A (en) | 1987-11-05 | 1989-08-15 | Texas Instruments Incorporated | Global event qualification system |
US6304987B1 (en) | 1995-06-07 | 2001-10-16 | Texas Instruments Incorporated | Integrated test circuit |
EP0382360B1 (de) * | 1989-02-08 | 1997-03-19 | Texas Instruments Incorporated | Durch Ereigniss befähigte Prüfarchitektur für integrierte Schaltungen |
US5483518A (en) | 1992-06-17 | 1996-01-09 | Texas Instruments Incorporated | Addressable shadow port and protocol for serial bus networks |
US5103450A (en) * | 1989-02-08 | 1992-04-07 | Texas Instruments Incorporated | Event qualified testing protocols for integrated circuits |
US5001713A (en) * | 1989-02-08 | 1991-03-19 | Texas Instruments Incorporated | Event qualified testing architecture for integrated circuits |
US5353308A (en) * | 1990-08-06 | 1994-10-04 | Texas Instruments Incorporated | Event qualified test methods and circuitry |
JP3005250B2 (ja) * | 1989-06-30 | 2000-01-31 | テキサス インスツルメンツ インコーポレイテツド | バスモニター集積回路 |
US5805792A (en) * | 1989-07-31 | 1998-09-08 | Texas Instruments Incorporated | Emulation devices, systems, and methods |
US6675333B1 (en) | 1990-03-30 | 2004-01-06 | Texas Instruments Incorporated | Integrated circuit with serial I/O controller |
FR2665593A1 (fr) * | 1990-08-03 | 1992-02-07 | Alcatel Radiotelephone | Circuit integre comprenant une cellule standard, une cellule d'application et une cellule de test. |
EP0470802B1 (de) * | 1990-08-06 | 1997-06-18 | Texas Instruments Incorporated | Durch Ereignis befähigte Prüfverfahren und Schaltungen |
KR100217535B1 (ko) * | 1990-08-06 | 1999-09-01 | 윌리엄 비. 켐플러 | 이벤트 한정 검사 아키텍춰 |
WO1992013281A1 (en) * | 1991-01-22 | 1992-08-06 | Vlsi Technology, Inc. | Method to reduce test vectors/test time in devices using equivalent blocks |
US5448166A (en) * | 1992-01-03 | 1995-09-05 | Hewlett-Packard Company | Powered testing of mixed conventional/boundary-scan logic |
US5260649A (en) * | 1992-01-03 | 1993-11-09 | Hewlett-Packard Company | Powered testing of mixed conventional/boundary-scan logic |
JP3563750B2 (ja) * | 1992-10-16 | 2004-09-08 | テキサス インスツルメンツ インコーポレイテツド | アナログ回路のための走査に基づく試験 |
US6101457A (en) * | 1992-10-29 | 2000-08-08 | Texas Instruments Incorporated | Test access port |
US5969538A (en) | 1996-10-31 | 1999-10-19 | Texas Instruments Incorporated | Semiconductor wafer with interconnect between dies for testing and a process of testing |
US6260165B1 (en) | 1996-10-18 | 2001-07-10 | Texas Instruments Incorporated | Accelerating scan test by re-using response data as stimulus data |
US6408413B1 (en) * | 1998-02-18 | 2002-06-18 | Texas Instruments Incorporated | Hierarchical access of test access ports in embedded core integrated circuits |
US6405335B1 (en) | 1998-02-25 | 2002-06-11 | Texas Instruments Incorporated | Position independent testing of circuits |
US6560734B1 (en) | 1998-06-19 | 2003-05-06 | Texas Instruments Incorporated | IC with addressable test port |
US6519729B1 (en) | 1998-06-27 | 2003-02-11 | Texas Instruments Incorporated | Reduced power testing with equally divided scan paths |
US6728915B2 (en) | 2000-01-10 | 2004-04-27 | Texas Instruments Incorporated | IC with shared scan cells selectively connected in scan path |
US6769080B2 (en) | 2000-03-09 | 2004-07-27 | Texas Instruments Incorporated | Scan circuit low power adapter with counter |
DE102004044813A1 (de) * | 2004-09-16 | 2006-03-23 | Robert Bosch Gmbh | Verfahren zum Testen eines integrierten Schaltkreises |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4023142A (en) * | 1975-04-14 | 1977-05-10 | International Business Machines Corporation | Common diagnostic bus for computer systems to enable testing concurrently with normal system operation |
US4513418A (en) * | 1982-11-08 | 1985-04-23 | International Business Machines Corporation | Simultaneous self-testing system |
JPS60140834A (ja) * | 1983-12-28 | 1985-07-25 | Nec Corp | テスト回路内蔵型半導体集積回路 |
US4857835A (en) | 1987-11-05 | 1989-08-15 | Texas Instruments Incorporated | Global event qualification system |
-
1987
- 1987-11-05 US US07/117,114 patent/US4857835A/en not_active Expired - Lifetime
-
1988
- 1988-11-04 DE DE3852862T patent/DE3852862T2/de not_active Expired - Fee Related
- 1988-11-04 EP EP88310404A patent/EP0315475B1/de not_active Expired - Lifetime
- 1988-11-04 JP JP63279163A patent/JP2873233B2/ja not_active Expired - Fee Related
- 1988-11-04 KR KR1019880014469A patent/KR970005390B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE3852862D1 (de) | 1995-03-09 |
EP0315475A2 (de) | 1989-05-10 |
KR890008570A (ko) | 1989-07-12 |
EP0315475A3 (de) | 1991-02-27 |
KR970005390B1 (ko) | 1997-04-15 |
US4857835A (en) | 1989-08-15 |
JPH02263176A (ja) | 1990-10-25 |
JP2873233B2 (ja) | 1999-03-24 |
EP0315475B1 (de) | 1995-01-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |