DE3786070D1 - Umhuellte halbleiteranordnung. - Google Patents

Umhuellte halbleiteranordnung.

Info

Publication number
DE3786070D1
DE3786070D1 DE8787311419T DE3786070T DE3786070D1 DE 3786070 D1 DE3786070 D1 DE 3786070D1 DE 8787311419 T DE8787311419 T DE 8787311419T DE 3786070 T DE3786070 T DE 3786070T DE 3786070 D1 DE3786070 D1 DE 3786070D1
Authority
DE
Germany
Prior art keywords
semiconductor arrangement
coated semiconductor
coated
arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787311419T
Other languages
English (en)
Other versions
DE3786070T2 (de
Inventor
Yasuhiro C O Patent Div Yamaji
Kenji C O Patent Div Takahashi
Seiichi C O Patent Divi Hirata
Toshiharu C O Patent D Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3786070D1 publication Critical patent/DE3786070D1/de
Publication of DE3786070T2 publication Critical patent/DE3786070T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE87311419T 1986-12-26 1987-12-23 Umhüllte Halbleiteranordnung. Expired - Lifetime DE3786070T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31375486 1986-12-26

Publications (2)

Publication Number Publication Date
DE3786070D1 true DE3786070D1 (de) 1993-07-08
DE3786070T2 DE3786070T2 (de) 1994-01-05

Family

ID=18045132

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87311419T Expired - Lifetime DE3786070T2 (de) 1986-12-26 1987-12-23 Umhüllte Halbleiteranordnung.

Country Status (3)

Country Link
US (1) US4855807A (de)
EP (1) EP0273725B1 (de)
DE (1) DE3786070T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350758A (ja) * 1989-07-18 1991-03-05 Toshiba Corp 樹脂封止型半導体装置
US5021864A (en) * 1989-09-05 1991-06-04 Micron Technology, Inc. Die-mounting paddle for mechanical stress reduction in plastic IC packages
JP2585830B2 (ja) * 1990-03-28 1997-02-26 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JP2890662B2 (ja) * 1990-04-25 1999-05-17 ソニー株式会社 樹脂封止型半導体装置の製造方法とそれに用いるリードフレーム
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions
JP3078860B2 (ja) * 1991-02-18 2000-08-21 株式会社デンソー 金属部材の樹脂インサート成形方法
US5214846A (en) * 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips
US5210375A (en) * 1991-06-28 1993-05-11 Vlsi Technology, Inc. Electronic device package--carrier assembly ready to be mounted onto a substrate
US5550323A (en) * 1991-08-28 1996-08-27 Lsi Logic Corporation Mounting of electronic devices
JPH05144982A (ja) * 1991-11-19 1993-06-11 Nippon Precision Circuits Kk 集積回路装置
US5512710A (en) * 1992-08-21 1996-04-30 Cts Corporation Multilayer package with second layer via test connections
US5686698A (en) * 1994-06-30 1997-11-11 Motorola, Inc. Package for electrical components having a molded structure with a port extending into the molded structure
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
US6589820B1 (en) 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6610924B1 (en) * 2000-07-25 2003-08-26 Advanced Semiconductor Engineering, Inc. Semiconductor package
US6483044B1 (en) * 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
TW525274B (en) * 2001-03-05 2003-03-21 Samsung Electronics Co Ltd Ultra thin semiconductor package having different thickness of die pad and leads, and method for manufacturing the same
US20040113240A1 (en) 2002-10-11 2004-06-17 Wolfgang Hauser An electronic component with a leadframe
US20080052878A1 (en) * 2006-08-31 2008-03-06 Lewis Jeffrey C Fastener Clip with Seal
US7833456B2 (en) 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece
DE102007019096B4 (de) * 2007-04-23 2015-03-12 Continental Automotive Gmbh Elektronikgehäuse
GB0714034D0 (en) * 2007-07-18 2007-08-29 Deepstream Technologies Ltd Improvements in and relating to manufacture of electrical circuits for electrical components
US11744020B2 (en) * 2021-11-30 2023-08-29 Texas Instruments Incorporated Mechanically bridged SMD interconnects for electronic devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL189379C (nl) * 1977-05-05 1993-03-16 Richardus Henricus Johannes Fi Werkwijze voor inkapselen van micro-elektronische elementen.
JPS5577160A (en) * 1978-12-07 1980-06-10 Nec Corp Semiconductor device
JPS5879739A (ja) * 1981-11-05 1983-05-13 Toshiba Corp 半導体外囲器
JPS59208764A (ja) * 1983-05-12 1984-11-27 Clarion Co Ltd 半導体装置
JPS6129157A (ja) * 1984-07-19 1986-02-10 Seiko Epson Corp 半導体装置
JPS61184855A (ja) * 1985-02-13 1986-08-18 Oki Electric Ind Co Ltd 樹脂封止形半導体装置
JPS61191055A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 樹脂封止型半導体装置
JPH0642483B2 (ja) * 1985-03-13 1994-06-01 松下電子工業株式会社 金属配線層の形成方法
JPS6242548A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd 半導体装置
JPS61166052A (ja) * 1986-01-20 1986-07-26 Hitachi Ltd 樹脂モールド半導体デバイス

Also Published As

Publication number Publication date
DE3786070T2 (de) 1994-01-05
EP0273725A3 (en) 1988-08-31
EP0273725A2 (de) 1988-07-06
EP0273725B1 (de) 1993-06-02
US4855807A (en) 1989-08-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)