DE3781794D1 - Vorrichtung und verfahren zum versehen eines cachespeichers mit einer schreiboperation mit zwei systemtaktzyklen. - Google Patents

Vorrichtung und verfahren zum versehen eines cachespeichers mit einer schreiboperation mit zwei systemtaktzyklen.

Info

Publication number
DE3781794D1
DE3781794D1 DE8787901788T DE3781794T DE3781794D1 DE 3781794 D1 DE3781794 D1 DE 3781794D1 DE 8787901788 T DE8787901788 T DE 8787901788T DE 3781794 T DE3781794 T DE 3781794T DE 3781794 D1 DE3781794 D1 DE 3781794D1
Authority
DE
Germany
Prior art keywords
providing
cache memory
write operation
system clock
clock cycles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787901788T
Other languages
English (en)
Other versions
DE3781794T2 (de
Inventor
E Stewart
J Flahive
B Keller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE3781794D1 publication Critical patent/DE3781794D1/de
Application granted granted Critical
Publication of DE3781794T2 publication Critical patent/DE3781794T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8787901788T 1986-01-29 1987-01-29 Vorrichtung und verfahren zum versehen eines cachespeichers mit einer schreiboperation mit zwei systemtaktzyklen. Expired - Lifetime DE3781794T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/823,805 US4755936A (en) 1986-01-29 1986-01-29 Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
PCT/US1987/000176 WO1987004823A1 (en) 1986-01-29 1987-01-29 Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles

Publications (2)

Publication Number Publication Date
DE3781794D1 true DE3781794D1 (de) 1992-10-22
DE3781794T2 DE3781794T2 (de) 1993-04-22

Family

ID=25239776

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787901788T Expired - Lifetime DE3781794T2 (de) 1986-01-29 1987-01-29 Vorrichtung und verfahren zum versehen eines cachespeichers mit einer schreiboperation mit zwei systemtaktzyklen.

Country Status (7)

Country Link
US (1) US4755936A (de)
EP (1) EP0292501B1 (de)
JP (1) JPH0668736B2 (de)
AU (1) AU7032687A (de)
CA (1) CA1277044C (de)
DE (1) DE3781794T2 (de)
WO (1) WO1987004823A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184753A (ja) * 1984-10-01 1986-04-30 Hitachi Ltd バツフアメモリ
US5034885A (en) * 1988-03-15 1991-07-23 Kabushiki Kaisha Toshiba Cache memory device with fast data-write capacity
US5123097A (en) * 1989-01-05 1992-06-16 Bull Hn Information Systems Inc. Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
US5148537A (en) * 1989-05-02 1992-09-15 Belsan Jay S Method and apparatus for effecting an intra-cache data transfer
JPH077356B2 (ja) * 1989-05-19 1995-01-30 株式会社東芝 パイプライン方式のマイクロプロセッサ
EP0400851A3 (de) * 1989-06-02 1992-10-21 Hewlett-Packard Company Leistungsfähiger Cache-Speicher mit Speicherpuffer
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
EP0442690A3 (en) * 1990-02-13 1992-11-19 Hewlett-Packard Company Data cache store buffer for high performance computer
US5450564A (en) * 1990-05-04 1995-09-12 Unisys Corporation Method and apparatus for cache memory access with separate fetch and store queues
US5257377A (en) * 1991-04-01 1993-10-26 Xerox Corporation Process for automatically migrating a subset of updated files from the boot disk to the replicated disks
GB2271204B (en) * 1992-10-01 1996-01-03 Digital Equipment Int Digital system memory access
US5388226A (en) * 1992-10-05 1995-02-07 Motorola, Inc. Method and apparatus for accessing a register in a data processing system
US6151661A (en) * 1994-03-03 2000-11-21 International Business Machines Corporation Cache memory storage space management system and method
DE69530720T2 (de) * 1994-03-09 2003-11-27 Sun Microsystems Inc Verzögertes Cachespeicherschreiben eines Speicherungsbefehls
US6076150A (en) * 1995-08-10 2000-06-13 Lsi Logic Corporation Cache controller with improved instruction and data forwarding during refill operation
US5987578A (en) * 1996-07-01 1999-11-16 Sun Microsystems, Inc. Pipelining to improve the interface of memory devices
US6032226A (en) * 1997-04-14 2000-02-29 International Business Machines Corporation Method and apparatus for layering cache and architectural specific functions to expedite multiple design
US6061762A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Apparatus and method for separately layering cache and architectural specific functions in different operational controllers
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
US6360307B1 (en) 1998-06-18 2002-03-19 Cypress Semiconductor Corporation Circuit architecture and method of writing data to a memory
US7962698B1 (en) 2005-10-03 2011-06-14 Cypress Semiconductor Corporation Deterministic collision detection

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
JPS53134335A (en) * 1977-04-28 1978-11-22 Fujitsu Ltd Memory control system
US4245304A (en) * 1978-12-11 1981-01-13 Honeywell Information Systems Inc. Cache arrangement utilizing a split cycle mode of operation
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
JPS5685168A (en) * 1979-12-13 1981-07-11 Fujitsu Ltd Access control system for main storage
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
EP0039227A3 (en) * 1980-04-25 1982-09-01 Data General Corporation Data processing system
JPS5750380A (en) * 1980-09-09 1982-03-24 Mitsubishi Electric Corp Writing method of buffer storage device
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4486856A (en) * 1982-05-10 1984-12-04 Teletype Corporation Cache memory and control circuit
US4682281A (en) * 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
US4612612A (en) * 1983-08-30 1986-09-16 Amdahl Corporation Virtually addressed cache
US4573116A (en) * 1983-12-20 1986-02-25 Honeywell Information Systems Inc. Multiword data register array having simultaneous read-write capability
US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller
JPS615357A (ja) * 1984-06-07 1986-01-11 Fujitsu Ltd デ−タ処理装置

Also Published As

Publication number Publication date
EP0292501B1 (de) 1992-09-16
JPH01500377A (ja) 1989-02-09
AU7032687A (en) 1987-08-25
US4755936A (en) 1988-07-05
DE3781794T2 (de) 1993-04-22
EP0292501A1 (de) 1988-11-30
CA1277044C (en) 1990-11-27
JPH0668736B2 (ja) 1994-08-31
WO1987004823A1 (en) 1987-08-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, 80538 MUENCHEN