DE3774488D1 - Verfahren zur routen-festlegung. - Google Patents

Verfahren zur routen-festlegung.

Info

Publication number
DE3774488D1
DE3774488D1 DE8787303026T DE3774488T DE3774488D1 DE 3774488 D1 DE3774488 D1 DE 3774488D1 DE 8787303026 T DE8787303026 T DE 8787303026T DE 3774488 T DE3774488 T DE 3774488T DE 3774488 D1 DE3774488 D1 DE 3774488D1
Authority
DE
Germany
Prior art keywords
procedure
determining routes
routes
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787303026T
Other languages
English (en)
Inventor
Serge Fournier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Application granted granted Critical
Publication of DE3774488D1 publication Critical patent/DE3774488D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE8787303026T 1986-06-05 1987-04-07 Verfahren zur routen-festlegung. Expired - Fee Related DE3774488D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/870,887 US4777606A (en) 1986-06-05 1986-06-05 Method for deriving an interconnection route between elements in an interconnection medium

Publications (1)

Publication Number Publication Date
DE3774488D1 true DE3774488D1 (de) 1991-12-19

Family

ID=25356258

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787303026T Expired - Fee Related DE3774488D1 (de) 1986-06-05 1987-04-07 Verfahren zur routen-festlegung.

Country Status (5)

Country Link
US (1) US4777606A (de)
EP (1) EP0248513B1 (de)
JP (1) JPH0786881B2 (de)
CA (1) CA1253604A (de)
DE (1) DE3774488D1 (de)

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JP2564344B2 (ja) * 1987-12-23 1996-12-18 株式会社日立製作所 半導体集積回路の設計方式
US5119317A (en) * 1988-03-16 1992-06-02 Kabushiki Kaisha Toshiba Routing method and system
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
DE3935418A1 (de) * 1988-10-24 1990-04-26 Hitachi Ltd Verfahren und vorrichtung zur bestimmung von verdrahtungsmustern
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5032991A (en) * 1988-12-14 1991-07-16 At&T Ball Laboratories Method for routing conductive paths
US5206815A (en) * 1989-01-13 1993-04-27 Vlsi Technology, Inc. Method for arranging modules in an integrated circuit
US5168342A (en) * 1989-01-30 1992-12-01 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method of the same
US5353243A (en) * 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5369593A (en) * 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5309372A (en) * 1989-07-17 1994-05-03 Kawasaki Steel Corp. System and method for determining routes between circuit blocks of a programmable logic device by determining a load pin which is closest to the center of gravity of a plurality of load pins
JPH03138961A (ja) * 1989-10-24 1991-06-13 Fujitsu Ltd 配線パターン決定方式
JPH03238556A (ja) * 1990-02-15 1991-10-24 Fuji Photo Film Co Ltd Ｃａｄシステム
US5309370A (en) * 1990-12-13 1994-05-03 Vlsi Technology, Inc. Method for placement of connectors used interconnecting circuit components in an integrated circuit
US5634093A (en) * 1991-01-30 1997-05-27 Kabushiki Kaisha Toshiba Method and CAD system for designing wiring patterns using predetermined rules
JP2759573B2 (ja) * 1992-01-23 1998-05-28 株式会社日立製作所 回路基板の配線パターン決定方法
US5475830A (en) * 1992-01-31 1995-12-12 Quickturn Design Systems, Inc. Structure and method for providing a reconfigurable emulation circuit without hold time violations
US5360767A (en) * 1993-04-12 1994-11-01 International Business Machines Corporation Method for assigning pins to connection points
US5648912A (en) * 1993-04-12 1997-07-15 International Business Machines Corporation Interconnection resource assignment method for differential current switch nets
US5625568A (en) * 1993-12-22 1997-04-29 Vlsi Technology, Inc. Method and apparatus for compacting integrated circuits with standard cell architectures
EP0741883A4 (de) * 1994-01-25 1997-02-05 Advantage Logic Inc Gerät und verfahren zur mittelaufteilung für verbindungen
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5636129A (en) * 1994-04-20 1997-06-03 Her; One-Hsiow A. Electrical routing through fixed sized module and variable sized channel grids
US5638288A (en) * 1994-08-24 1997-06-10 Lsi Logic Corporation Separable cells having wiring channels for routing signals between surrounding cells
US5587923A (en) * 1994-09-07 1996-12-24 Lsi Logic Corporation Method for estimating routability and congestion in a cell placement for integrated circuit chip
US5859781A (en) * 1994-09-13 1999-01-12 Lsi Logic Corporation Method and apparatus for computing minimum wirelength position (MWP) for cell in cell placement for integrated circuit chip
US5677847A (en) * 1995-12-05 1997-10-14 International Business Machines Corporation Method and apparatus for designing a module
US6353918B1 (en) 1996-03-15 2002-03-05 The Arizona Board Of Regents On Behalf Of The University Of Arizona Interconnection routing system
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US5818730A (en) * 1996-12-05 1998-10-06 Xilinx, Inc. FPGA one turn routing structure and method using minimum diffusion area
US5828230A (en) * 1997-01-09 1998-10-27 Xilinx, Inc. FPGA two turn routing structure with lane changing and minimum diffusion area
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
JPH11110434A (ja) * 1997-10-07 1999-04-23 Fujitsu Ltd プリント板パターン設計装置
US6266802B1 (en) * 1997-10-27 2001-07-24 International Business Machines Corporation Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm
US6182272B1 (en) * 1998-07-16 2001-01-30 Lsi Logic Corporation Metal layer assignment
WO2001024111A1 (en) * 1999-09-30 2001-04-05 Routech, Inc. Automatic routing system for pc board design
JP2002009160A (ja) * 2000-06-26 2002-01-11 Nec Microsystems Ltd 半導体集積回路の自動レイアウト方法、この方法で製造した半導体集積回路及びこの方法を記録した記録媒体
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7055120B2 (en) 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US6957410B2 (en) * 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US7441220B2 (en) * 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US7594196B2 (en) * 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US7036105B1 (en) 2002-01-22 2006-04-25 Cadence Design Systems, Inc. Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's
US7013451B1 (en) 2002-01-22 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for performing routability checking
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US7069531B1 (en) * 2002-07-15 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for identifying a path between source and target states in a space with more than two dimensions
US7047512B1 (en) 2002-06-04 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space
US7051298B1 (en) 2002-06-04 2006-05-23 Cadence Design Systems, Inc. Method and apparatus for specifying a distance between an external state and a set of states in space
US7073151B1 (en) 2002-06-04 2006-07-04 Cadence Design Systems, Inc. Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space
US6996789B2 (en) * 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7003752B2 (en) * 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US6988257B2 (en) * 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7010771B2 (en) * 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7047513B2 (en) * 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7093221B2 (en) * 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7171635B2 (en) * 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US6892369B2 (en) * 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US7216308B2 (en) * 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7624367B2 (en) 2002-11-18 2009-11-24 Cadence Design Systems, Inc. Method and system for routing
US7080342B2 (en) * 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
TWI220268B (en) * 2003-09-17 2004-08-11 Faraday Tech Corp Method for programming a routing layout design through one via layer
TWI220288B (en) * 2003-10-13 2004-08-11 Powerchip Semiconductor Corp Method of defect control
US7373628B1 (en) 2004-06-01 2008-05-13 Pulsic Limited Method of automatically routing nets using a Steiner tree
US7784010B1 (en) 2004-06-01 2010-08-24 Pulsic Limited Automatic routing system with variable width interconnect
US7131096B1 (en) 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
US8095903B2 (en) * 2004-06-01 2012-01-10 Pulsic Limited Automatically routing nets with variable spacing
US7707537B2 (en) * 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US7412682B2 (en) * 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7340711B2 (en) * 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US7257797B1 (en) 2004-06-07 2007-08-14 Pulsic Limited Method of automatic shape-based routing of interconnects in spines for integrated circuit design
JP4410088B2 (ja) * 2004-11-29 2010-02-03 富士通株式会社 半導体装置の設計支援方法、プログラム及び装置
US9245082B2 (en) * 2005-06-21 2016-01-26 Pulsic Limited High-speed shape-based router
US7603644B2 (en) * 2005-06-24 2009-10-13 Pulsic Limited Integrated circuit routing and compaction
US7363607B2 (en) 2005-11-08 2008-04-22 Pulsic Limited Method of automatically routing nets according to parasitic constraint rules
US8250514B1 (en) 2006-07-13 2012-08-21 Cadence Design Systems, Inc. Localized routing direction
US20080109782A1 (en) * 2006-10-18 2008-05-08 Utstarcom, Inc. Method and system for pin assignment
US8458636B1 (en) 2009-03-18 2013-06-04 Pulsic Limited Filling vacant areas of an integrated circuit design

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US4495559A (en) * 1981-11-02 1985-01-22 International Business Machines Corporation Optimization of an organization of many discrete elements
US4510616A (en) * 1982-01-19 1985-04-09 The Environmental Research Institute Of Michigan Design rule checking using serial neighborhood processors
US4441207A (en) * 1982-01-19 1984-04-03 Environmental Research Institute Of Michigan Design rule checking using serial neighborhood processors
GB2131577B (en) * 1982-09-04 1985-10-02 Marconi Co Ltd Circuit route planning
US4500963A (en) * 1982-11-29 1985-02-19 The United States Of America As Represented By The Secretary Of The Army Automatic layout program for hybrid microcircuits (HYPAR)
US4593363A (en) * 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US4615011A (en) * 1983-12-19 1986-09-30 Ibm Iterative method for establishing connections and resulting product
US4636965A (en) * 1984-05-10 1987-01-13 Rca Corporation Routing method in computer-aided-customization of universal arrays and resulting integrated circuit
US4613941A (en) * 1985-07-02 1986-09-23 The United States Of America As Represented By The Secretary Of The Army Routing method in computer aided customization of a two level automated universal array

Also Published As

Publication number Publication date
JPH0786881B2 (ja) 1995-09-20
CA1253604A (en) 1989-05-02
EP0248513A2 (de) 1987-12-09
EP0248513B1 (de) 1991-11-13
US4777606A (en) 1988-10-11
JPS62291998A (ja) 1987-12-18
EP0248513A3 (en) 1989-02-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee