DE3717440A1 - Halbleiter-plaettchen und verfahren zu seiner herstellung - Google Patents

Halbleiter-plaettchen und verfahren zu seiner herstellung

Info

Publication number
DE3717440A1
DE3717440A1 DE19873717440 DE3717440A DE3717440A1 DE 3717440 A1 DE3717440 A1 DE 3717440A1 DE 19873717440 DE19873717440 DE 19873717440 DE 3717440 A DE3717440 A DE 3717440A DE 3717440 A1 DE3717440 A1 DE 3717440A1
Authority
DE
Germany
Prior art keywords
blocking film
film
semiconductor wafer
semiconductor
wafer according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873717440
Other languages
German (de)
English (en)
Other versions
DE3717440C2 (https=
Inventor
Tetsujiro Yoshiharu
Haruo Kamise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Kyushu Electronic Metal Co Ltd
Osaka Titanium Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Electronic Metal Co Ltd, Osaka Titanium Co Ltd filed Critical Kyushu Electronic Metal Co Ltd
Priority to DE19873717440 priority Critical patent/DE3717440A1/de
Priority to US07/214,501 priority patent/US4925809A/en
Publication of DE3717440A1 publication Critical patent/DE3717440A1/de
Application granted granted Critical
Publication of DE3717440C2 publication Critical patent/DE3717440C2/de
Priority to US07/742,560 priority patent/US5225235A/en
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/15—Diffusion of dopants within, into or out of semiconductor bodies or layers from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
DE19873717440 1987-05-18 1987-05-23 Halbleiter-plaettchen und verfahren zu seiner herstellung Granted DE3717440A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE19873717440 DE3717440A1 (de) 1987-05-23 1987-05-23 Halbleiter-plaettchen und verfahren zu seiner herstellung
US07/214,501 US4925809A (en) 1987-05-23 1988-07-01 Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor
US07/742,560 US5225235A (en) 1987-05-18 1991-08-05 Semiconductor wafer and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19873717440 DE3717440A1 (de) 1987-05-23 1987-05-23 Halbleiter-plaettchen und verfahren zu seiner herstellung

Publications (2)

Publication Number Publication Date
DE3717440A1 true DE3717440A1 (de) 1988-12-01
DE3717440C2 DE3717440C2 (https=) 1991-01-31

Family

ID=6328274

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873717440 Granted DE3717440A1 (de) 1987-05-18 1987-05-23 Halbleiter-plaettchen und verfahren zu seiner herstellung

Country Status (1)

Country Link
DE (1) DE3717440A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0529888A1 (en) * 1991-08-22 1993-03-03 AT&T Corp. Removal of substrate perimeter material
EP0667637A3 (en) * 1994-02-12 1996-11-06 Shinetsu Handotai Kk Semiconductor single crystalline substrate and method for production thereof.
EP0825639A3 (en) * 1996-08-19 1999-05-26 Shin-Etsu Handotai Company Limited Silicon wafer and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J. Electrochem. Soc., Nov. 1969, pp. 1561-1565 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0529888A1 (en) * 1991-08-22 1993-03-03 AT&T Corp. Removal of substrate perimeter material
US5425846A (en) * 1991-08-22 1995-06-20 At&T Corp. Removal of substrate perimeter material
US5989985A (en) * 1994-01-12 1999-11-23 Shin-Etsu Handotai Co., Ltd. Semiconductor single crystalline substrate and method for production thereof
EP0667637A3 (en) * 1994-02-12 1996-11-06 Shinetsu Handotai Kk Semiconductor single crystalline substrate and method for production thereof.
EP0863541A1 (en) * 1994-02-12 1998-09-09 Shin-Etsu Handotai Company Limited Method for the production of a semiconductor single crystalline substrate having a chamfer and a protecting film
EP0825639A3 (en) * 1996-08-19 1999-05-26 Shin-Etsu Handotai Company Limited Silicon wafer and method of manufacturing the same
US5998283A (en) * 1996-08-19 1999-12-07 Shin-Etsu Handotai Co., Ltd. Silicon wafer having plasma CVD gettering layer with components/composition changing in depth-wise direction and method of manufacturing the silicon wafer

Also Published As

Publication number Publication date
DE3717440C2 (https=) 1991-01-31

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SUMITOMO METAL INDUSTRIES, LTD., OSAKA, JP

8327 Change in the person/name/address of the patent owner

Owner name: SUMITOMO MITSUBISHI SILICON CORP., TOKIO/TOYKO, JP