DE3689712D1 - NOR-Gatter mit Festlegung des niedrigen logischen Ausgangswertes. - Google Patents

NOR-Gatter mit Festlegung des niedrigen logischen Ausgangswertes.

Info

Publication number
DE3689712D1
DE3689712D1 DE86201028T DE3689712T DE3689712D1 DE 3689712 D1 DE3689712 D1 DE 3689712D1 DE 86201028 T DE86201028 T DE 86201028T DE 3689712 T DE3689712 T DE 3689712T DE 3689712 D1 DE3689712 D1 DE 3689712D1
Authority
DE
Germany
Prior art keywords
definition
gate
output value
low logic
logic output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE86201028T
Other languages
English (en)
Other versions
DE3689712T2 (de
Inventor
Scott Timothy Becker
Michael John Bergman
Shueh-Mien Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3689712D1 publication Critical patent/DE3689712D1/de
Publication of DE3689712T2 publication Critical patent/DE3689712T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE3689712T 1985-06-17 1986-06-16 NOR-Gatter mit Festlegung des niedrigen logischen Ausgangswertes. Expired - Fee Related DE3689712T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/745,475 US4641046A (en) 1985-06-17 1985-06-17 NOR gate with logical low output clamp

Publications (2)

Publication Number Publication Date
DE3689712D1 true DE3689712D1 (de) 1994-04-21
DE3689712T2 DE3689712T2 (de) 1994-09-22

Family

ID=24996855

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3689712T Expired - Fee Related DE3689712T2 (de) 1985-06-17 1986-06-16 NOR-Gatter mit Festlegung des niedrigen logischen Ausgangswertes.

Country Status (3)

Country Link
US (1) US4641046A (de)
EP (1) EP0206405B1 (de)
DE (1) DE3689712T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728827A (en) * 1986-12-03 1988-03-01 Advanced Micro Devices, Inc. Static PLA or ROM circuit with self-generated precharge
US4806785A (en) * 1988-02-17 1989-02-21 International Business Machines Corporation Half current switch with feedback
US5059837A (en) * 1989-02-13 1991-10-22 Ibm Data dependent variable time delay circuit
US5182468A (en) * 1989-02-13 1993-01-26 Ibm Corporation Current limiting clamp circuit
US5049767A (en) * 1989-05-01 1991-09-17 Honeywell Inc. Shared inverter outputs delay system
US5045723A (en) * 1990-07-31 1991-09-03 International Business Machines Corporation Multiple input CMOS logic circuits
JPH04317219A (ja) * 1991-04-17 1992-11-09 Mitsubishi Electric Corp 出力回路
US5541528A (en) * 1995-08-25 1996-07-30 Hal Computer Systems, Inc. CMOS buffer circuit having increased speed
US5654652A (en) * 1995-09-27 1997-08-05 Cypress Semiconductor Corporation High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1063025B (it) * 1975-04-29 1985-02-11 Siemens Ag Disposizione circuitale logica integrata e programmabile
US4123669A (en) * 1977-09-08 1978-10-31 International Business Machines Corporation Logical OR circuit for programmed logic arrays
JPS5824874B2 (ja) * 1979-02-07 1983-05-24 富士通株式会社 センス回路
JPS57192122A (en) * 1981-05-21 1982-11-26 Toshiba Corp Signal generating circuit
US4445051A (en) * 1981-06-26 1984-04-24 Burroughs Corporation Field effect current mode logic gate
US4471240A (en) * 1982-08-19 1984-09-11 Motorola, Inc. Power-saving decoder for memories
US4538075A (en) * 1983-09-07 1985-08-27 Advanced Micro Devices, Inc. High speed referenceless bipolar logic gate with minimum input current
US4617479B1 (en) * 1984-05-03 1993-09-21 Altera Semiconductor Corp. Programmable logic array device using eprom technology

Also Published As

Publication number Publication date
DE3689712T2 (de) 1994-09-22
US4641046A (en) 1987-02-03
EP0206405B1 (de) 1994-03-16
EP0206405A2 (de) 1986-12-30
EP0206405A3 (en) 1990-03-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8322 Nonbinding interest in granting licences declared
8339 Ceased/non-payment of the annual fee