DE3687085T2 - Mit hoher geschwindigkeit arbeitende kellerschaltung fuer ein datenregister in einem mikrorechner. - Google Patents

Mit hoher geschwindigkeit arbeitende kellerschaltung fuer ein datenregister in einem mikrorechner.

Info

Publication number
DE3687085T2
DE3687085T2 DE8686303631T DE3687085T DE3687085T2 DE 3687085 T2 DE3687085 T2 DE 3687085T2 DE 8686303631 T DE8686303631 T DE 8686303631T DE 3687085 T DE3687085 T DE 3687085T DE 3687085 T2 DE3687085 T2 DE 3687085T2
Authority
DE
Germany
Prior art keywords
cellar
speed
circuit
data register
micro computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686303631T
Other languages
English (en)
Other versions
DE3687085D1 (de
Inventor
Kenji Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3687085D1 publication Critical patent/DE3687085D1/de
Application granted granted Critical
Publication of DE3687085T2 publication Critical patent/DE3687085T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
DE8686303631T 1985-05-17 1986-05-13 Mit hoher geschwindigkeit arbeitende kellerschaltung fuer ein datenregister in einem mikrorechner. Expired - Fee Related DE3687085T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60105572A JPS61262922A (ja) 1985-05-17 1985-05-17 レジスタデ−タの高速スタツク回路

Publications (2)

Publication Number Publication Date
DE3687085D1 DE3687085D1 (de) 1992-12-17
DE3687085T2 true DE3687085T2 (de) 1993-03-18

Family

ID=14411235

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686303631T Expired - Fee Related DE3687085T2 (de) 1985-05-17 1986-05-13 Mit hoher geschwindigkeit arbeitende kellerschaltung fuer ein datenregister in einem mikrorechner.

Country Status (5)

Country Link
US (1) US4945469A (de)
EP (1) EP0202848B1 (de)
JP (1) JPS61262922A (de)
KR (1) KR900005553B1 (de)
DE (1) DE3687085T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244393A (ja) * 1987-03-30 1988-10-11 Nec Corp 並列入出力回路を有する記憶装置
JPS643739A (en) * 1987-06-26 1989-01-09 Toshiba Corp Information processor
EP0454606A3 (en) * 1990-04-23 1993-08-11 International Business Machines Corporation Digital processor with a pipelined architecture permitting an improved concurrent processing of multiple applications
US5546343A (en) * 1990-10-18 1996-08-13 Elliott; Duncan G. Method and apparatus for a single instruction operating multiple processors on a memory chip
KR960001273B1 (ko) * 1991-04-30 1996-01-25 가부시키가이샤 도시바 단일칩 마이크로컴퓨터
DE69231957T2 (de) 1991-10-21 2002-04-04 Toshiba Kawasaki Kk Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen
US5473271A (en) * 1993-02-09 1995-12-05 Dallas Semiconductor Corporation Microprocessor output driver
JP2993342B2 (ja) * 1993-12-27 1999-12-20 日本電気株式会社 マイクロプロセッサの制御方法
JPH08212185A (ja) * 1995-01-31 1996-08-20 Mitsubishi Electric Corp マイクロコンピュータ
US6058467A (en) * 1998-08-07 2000-05-02 Dallas Semiconductor Corporation Standard cell, 4-cycle, 8-bit microcontroller
KR100762264B1 (ko) 2005-06-14 2007-10-01 충남대학교산학협력단 지연 시간을 감소시키는 버스 매트릭스 구조

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602889A (en) * 1969-02-05 1971-08-31 Honeywell Inc Extended addressing for programmed data processor having improved register loading means
US3810114A (en) * 1971-12-29 1974-05-07 Tokyo Shibaura Electric Co Data processing system
FR121860A (de) * 1973-07-19
US4193127A (en) * 1979-01-02 1980-03-11 International Business Machines Corporation Simultaneous read/write cell
US4554645A (en) * 1983-03-10 1985-11-19 International Business Machines Corporation Multi-port register implementation
US4654780A (en) * 1984-06-05 1987-03-31 Burroughs Corporation Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

Also Published As

Publication number Publication date
JPS61262922A (ja) 1986-11-20
EP0202848B1 (de) 1992-11-11
KR860009341A (ko) 1986-12-22
DE3687085D1 (de) 1992-12-17
JPH046981B2 (de) 1992-02-07
EP0202848A2 (de) 1986-11-26
KR900005553B1 (ko) 1990-07-31
US4945469A (en) 1990-07-31
EP0202848A3 (en) 1988-08-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee