DE3685711D1 - Anordnung zur simulation von rechnerfunktionen von grossrechenanlagen. - Google Patents

Anordnung zur simulation von rechnerfunktionen von grossrechenanlagen.

Info

Publication number
DE3685711D1
DE3685711D1 DE8686902631T DE3685711T DE3685711D1 DE 3685711 D1 DE3685711 D1 DE 3685711D1 DE 8686902631 T DE8686902631 T DE 8686902631T DE 3685711 T DE3685711 T DE 3685711T DE 3685711 D1 DE3685711 D1 DE 3685711D1
Authority
DE
Germany
Prior art keywords
arrangement
simulating
functions
computer systems
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686902631T
Other languages
English (en)
Other versions
DE3685711T2 (de
Inventor
T Jennings
S Schibinger
J Kalemba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of DE3685711D1 publication Critical patent/DE3685711D1/de
Publication of DE3685711T2 publication Critical patent/DE3685711T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE8686902631T 1985-04-05 1986-04-02 Anordnung zur simulation von rechnerfunktionen von grossrechenanlagen. Expired - Fee Related DE3685711T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/720,573 US4819150A (en) 1985-04-05 1985-04-05 Array for simulating computer functions for large computer systems
PCT/US1986/000655 WO1986005900A1 (en) 1985-04-05 1986-04-02 An array for simulating computer functions for large computer systems

Publications (2)

Publication Number Publication Date
DE3685711D1 true DE3685711D1 (de) 1992-07-23
DE3685711T2 DE3685711T2 (de) 1993-01-21

Family

ID=24894496

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686902631T Expired - Fee Related DE3685711T2 (de) 1985-04-05 1986-04-02 Anordnung zur simulation von rechnerfunktionen von grossrechenanlagen.

Country Status (6)

Country Link
US (1) US4819150A (de)
EP (1) EP0217922B1 (de)
JP (1) JPS62502151A (de)
CA (1) CA1246743A (de)
DE (1) DE3685711T2 (de)
WO (1) WO1986005900A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060150A (en) * 1987-01-05 1991-10-22 Motorola, Inc. Process creation and termination monitors for use in a distributed message-based operating system
US5093920A (en) * 1987-06-25 1992-03-03 At&T Bell Laboratories Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
DE3855236D1 (de) * 1987-08-17 1996-05-30 Us Commerce Verfahren zur behandlung der bösartigen und autoimmunen krankheiten beim menschen
DE3808649A1 (de) * 1988-03-15 1989-10-05 Nixdorf Computer Ag Steuereinrichtung fuer ein elektrisches bzw. elektromechanisches geraet
JP3144950B2 (ja) * 1993-04-28 2001-03-12 富士通株式会社 論理シミュレーション方式
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5561795A (en) * 1994-05-13 1996-10-01 Unisys Corporation Method and apparatus for audit trail logging and data base recovery
US5920712A (en) * 1994-05-13 1999-07-06 Quickturn Design Systems, Inc. Emulation system having multiple emulator clock cycles per emulated clock cycle
GB9413127D0 (en) * 1994-06-30 1994-08-24 Philips Electronics Uk Ltd Data processing apparatus
US5838908A (en) * 1994-11-14 1998-11-17 Texas Instruments Incorporated Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays
US5561762A (en) * 1995-06-06 1996-10-01 Union Switch & Signal Inc. Malicious fault list generation method
US5923865A (en) * 1995-06-28 1999-07-13 Quickturn Design Systems, Inc. Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
US5819065A (en) * 1995-06-28 1998-10-06 Quickturn Design Systems, Inc. System and method for emulating memory
US5822564A (en) * 1996-06-03 1998-10-13 Quickturn Design Systems, Inc. Checkpointing in an emulation system
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
GB2336008B (en) * 1998-04-03 2000-11-08 Schlumberger Holdings Simulation system including a simulator and a case manager adapted for organizing data files
US6618698B1 (en) 1999-08-12 2003-09-09 Quickturn Design Systems, Inc. Clustered processors in an emulation engine
US7096174B2 (en) * 2001-07-17 2006-08-22 Carnegie Mellon University Systems, methods and computer program products for creating hierarchical equivalent circuit models
CA2490804C (en) 2002-06-28 2016-12-06 The Government Of The United States Of America As Represented By The Secretary Of The Department Of Health And Human Services Method of treating autoimmune diseases with interferon-beta and il-2r antagonist
US20070073999A1 (en) * 2005-09-28 2007-03-29 Verheyen Henry T Hardware acceleration system for logic simulation using shift register as local cache with path for bypassing shift register
US8589841B2 (en) * 2012-04-05 2013-11-19 International Business Machines Corporation Automatic parity checking identification

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2296221A1 (fr) 1974-12-27 1976-07-23 Ibm France Systeme de traitement du signal
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
JPS5975347A (ja) * 1982-10-21 1984-04-28 Toshiba Corp 論理回路のシミユレ−シヨン装置
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures

Also Published As

Publication number Publication date
WO1986005900A1 (en) 1986-10-09
EP0217922B1 (de) 1992-06-17
JPS62502151A (ja) 1987-08-20
DE3685711T2 (de) 1993-01-21
CA1246743A (en) 1988-12-13
US4819150A (en) 1989-04-04
EP0217922A1 (de) 1987-04-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee