DE3684237D1 - Pruefsystem mit hierarchischer architektur. - Google Patents

Pruefsystem mit hierarchischer architektur.

Info

Publication number
DE3684237D1
DE3684237D1 DE8686111770T DE3684237T DE3684237D1 DE 3684237 D1 DE3684237 D1 DE 3684237D1 DE 8686111770 T DE8686111770 T DE 8686111770T DE 3684237 T DE3684237 T DE 3684237T DE 3684237 D1 DE3684237 D1 DE 3684237D1
Authority
DE
Germany
Prior art keywords
test
pin
device under
per
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686111770T
Other languages
English (en)
Inventor
Ernest H Millham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3684237D1 publication Critical patent/DE3684237D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE8686111770T 1985-10-11 1986-08-26 Pruefsystem mit hierarchischer architektur. Expired - Fee Related DE3684237D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/786,428 US4682330A (en) 1985-10-11 1985-10-11 Hierarchical test system architecture

Publications (1)

Publication Number Publication Date
DE3684237D1 true DE3684237D1 (de) 1992-04-16

Family

ID=25138546

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686111770T Expired - Fee Related DE3684237D1 (de) 1985-10-11 1986-08-26 Pruefsystem mit hierarchischer architektur.

Country Status (5)

Country Link
US (1) US4682330A (de)
EP (1) EP0222084B1 (de)
JP (1) JPH0682147B2 (de)
CA (1) CA1251282A (de)
DE (1) DE3684237D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0337023A1 (de) * 1983-11-25 1989-10-18 Giordano Associates, Inc. Ausverdichtung von gespeicherten Prüfdaten für automatische Prüfsysteme
IE851998L (en) * 1985-08-14 1987-05-11 Francis Anthony Purcell Test apparatus for electronic equipment
US4763124A (en) * 1986-03-06 1988-08-09 Grumman Aerospace Corporation Signal distribution system hybrid relay controller/driver
CA1259680A (en) * 1986-05-06 1989-09-19 Mosaid Technologies Inc. Digital signal scrambler
US4730318A (en) * 1986-11-24 1988-03-08 International Business Machines Corporation Modular organized storage tester
US4856001A (en) * 1987-05-29 1989-08-08 Zehntel, Inc. Digital in-circuit tester having channel-memory earse-preventer
US5563524A (en) * 1989-05-19 1996-10-08 A.T.E. Solutions, Inc. Apparatus for testing electric circuits
US5151903A (en) * 1989-09-28 1992-09-29 Texas Instruments Incorporated High efficiency pattern sequence controller for automatic test equipment
US5127011A (en) * 1990-01-12 1992-06-30 International Business Machines Corporation Per-pin integrated circuit test system having n-bit interface
US5212443A (en) * 1990-09-05 1993-05-18 Schlumberger Technologies, Inc. Event sequencer for automatic test equipment
US5225772A (en) * 1990-09-05 1993-07-06 Schlumberger Technologies, Inc. Automatic test equipment system using pin slice architecture
US5195097A (en) * 1990-10-19 1993-03-16 International Business Machines Corporation High speed tester
US5293123A (en) * 1990-10-19 1994-03-08 Tandem Computers Incorporated Pseudo-Random scan test apparatus
US5421004A (en) * 1992-09-24 1995-05-30 International Business Machines Corporation Hierarchical testing environment
EP0592080A2 (de) * 1992-09-24 1994-04-13 International Business Machines Corporation Verfahren und Gerät für Kommunikation zwischen Prozessen in einem Multirechnersystem
US5345450A (en) * 1993-03-26 1994-09-06 Vlsi Technology, Inc. Method of compressing and decompressing simulation data for generating a test program for testing a logic device
US5872797A (en) * 1996-12-02 1999-02-16 International Business Machines Corporation Burn-in signal pattern generator
US5883905A (en) * 1997-02-18 1999-03-16 Schlumberger Technologies, Inc. Pattern generator with extended register programming
US5835506A (en) * 1997-04-29 1998-11-10 Credence Systems Corporation Single pass doublet mode integrated circuit tester
JP4238737B2 (ja) * 2004-02-09 2009-03-18 株式会社デンソー データ通信制御装置
US7506211B2 (en) * 2005-09-13 2009-03-17 International Business Machines Corporation Automated atomic system testing
US8295182B2 (en) * 2007-07-03 2012-10-23 Credence Systems Corporation Routed event test system and method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787669A (en) * 1972-06-30 1974-01-22 Ibm Test pattern generator
US3873818A (en) * 1973-10-29 1975-03-25 Ibm Electronic tester for testing devices having a high circuit density
US4044244A (en) * 1976-08-06 1977-08-23 International Business Machines Corporation Automatic tester for complex semiconductor components including combinations of logic, memory and analog devices and processes of testing thereof
US4070565A (en) * 1976-08-18 1978-01-24 Zehntel, Inc. Programmable tester method and apparatus
US4168527A (en) * 1978-02-17 1979-09-18 Winkler Dean A Analog and digital circuit tester
DE2839950B1 (de) * 1978-09-14 1979-10-25 Ibm Deutschland Einrichtung zur Feststellung der Laenge beliebiger Schieberegister
JPS5914840B2 (ja) * 1979-10-19 1984-04-06 日本電信電話株式会社 半導体メモリ試験用パタ−ン発生装置
US4433414A (en) * 1981-09-30 1984-02-21 Fairchild Camera And Instrument Corporation Digital tester local memory data storage system
US4493079A (en) * 1982-08-18 1985-01-08 Fairchild Camera & Instrument Corp. Method and system for selectively loading test data into test data storage means of automatic digital test equipment
US4598245B1 (en) * 1983-06-13 1993-11-16 Circuit tester having indirect counters

Also Published As

Publication number Publication date
JPH0682147B2 (ja) 1994-10-19
EP0222084B1 (de) 1992-03-11
EP0222084A3 (en) 1988-11-02
EP0222084A2 (de) 1987-05-20
JPS6288972A (ja) 1987-04-23
CA1251282A (en) 1989-03-14
US4682330A (en) 1987-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee