DE3672032D1 - Halbleitervorrichtung mit verringerter kapazitiver belastung und deren herstellungsverfahren. - Google Patents

Halbleitervorrichtung mit verringerter kapazitiver belastung und deren herstellungsverfahren.

Info

Publication number
DE3672032D1
DE3672032D1 DE8686113187T DE3672032T DE3672032D1 DE 3672032 D1 DE3672032 D1 DE 3672032D1 DE 8686113187 T DE8686113187 T DE 8686113187T DE 3672032 T DE3672032 T DE 3672032T DE 3672032 D1 DE3672032 D1 DE 3672032D1
Authority
DE
Germany
Prior art keywords
semiconductor device
production method
capacitive load
reduced capacitive
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686113187T
Other languages
English (en)
Inventor
Tatsuo C O Toshiba Hiy Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3672032D1 publication Critical patent/DE3672032D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE8686113187T 1985-09-25 1986-09-25 Halbleitervorrichtung mit verringerter kapazitiver belastung und deren herstellungsverfahren. Expired - Lifetime DE3672032D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60211557A JPS6272144A (ja) 1985-09-25 1985-09-25 半導体装置

Publications (1)

Publication Number Publication Date
DE3672032D1 true DE3672032D1 (de) 1990-07-19

Family

ID=16607774

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686113187T Expired - Lifetime DE3672032D1 (de) 1985-09-25 1986-09-25 Halbleitervorrichtung mit verringerter kapazitiver belastung und deren herstellungsverfahren.

Country Status (4)

Country Link
US (1) US4960725A (de)
EP (1) EP0220500B1 (de)
JP (1) JPS6272144A (de)
DE (1) DE3672032D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68916784T2 (de) * 1989-04-20 1995-01-05 Ibm Integrierte Schaltungspackung.
EP0412405A3 (en) * 1989-08-09 1991-09-18 National Semiconductor Corporation Method and apparatus for improvement of interconnection capacitance
US5262672A (en) * 1989-08-09 1993-11-16 National Semiconductor Corporation Apparatus for improvement of interconnection capacitance
US5107320A (en) * 1989-08-09 1992-04-21 National Semiconductor Corporation Method and apparatus for improvement of interconnection capacitance
US6380598B1 (en) 1994-12-20 2002-04-30 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
EP0718881B1 (de) * 1994-12-20 2003-07-16 STMicroelectronics, Inc. Isolierung durch aktive Transistoren mit geerdeten Torelektroden
DE69738012T2 (de) 1996-11-26 2007-12-13 Matsushita Electric Industrial Co., Ltd., Kadoma Halbleitervorrichtung und deren Herstellungsverfahren
DE69936175T2 (de) * 1998-11-04 2008-01-24 Lucent Technologies Inc. Induktivität oder Leiterbahn mit geringem Verlust in einer integrierten Schaltung
US6091630A (en) * 1999-09-10 2000-07-18 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
US6756619B2 (en) * 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
RU206227U1 (ru) * 2021-03-10 2021-09-01 Акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Кремниевый 3d конденсатор
RU205633U1 (ru) * 2021-03-15 2021-07-23 Акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Кремниевый конденсатор

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514398A1 (de) * 1965-02-09 1969-09-11 Siemens Ag Halbleiteranordnung
JPS5391591A (en) * 1977-01-21 1978-08-11 Mitsubishi Electric Corp Semiconductor device
US4290078A (en) * 1979-05-30 1981-09-15 Xerox Corporation High voltage MOSFET without field plate structure
US4442529A (en) * 1981-02-04 1984-04-10 At&T Bell Telephone Laboratories, Incorporated Power supply rejection characteristics of CMOS circuits
US4385947A (en) * 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation
JPS59145352A (ja) * 1983-02-03 1984-08-20 Mitsubishi Electric Corp 内燃機関のｅｇｒ制御装置
US4574467A (en) * 1983-08-31 1986-03-11 Solid State Scientific, Inc. N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel

Also Published As

Publication number Publication date
US4960725A (en) 1990-10-02
EP0220500A1 (de) 1987-05-06
EP0220500B1 (de) 1990-06-13
JPS6272144A (ja) 1987-04-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee