DE3587910D1 - Peripheres Interface-System. - Google Patents

Peripheres Interface-System.

Info

Publication number
DE3587910D1
DE3587910D1 DE3587910T DE3587910T DE3587910D1 DE 3587910 D1 DE3587910 D1 DE 3587910D1 DE 3587910 T DE3587910 T DE 3587910T DE 3587910 T DE3587910 T DE 3587910T DE 3587910 D1 DE3587910 D1 DE 3587910D1
Authority
DE
Germany
Prior art keywords
multiplexer
data
input
controller
storage area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3587910T
Other languages
English (en)
Other versions
DE3587910T2 (de
Inventor
Robert James Halford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cray Research LLC
Original Assignee
Cray Research LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cray Research LLC filed Critical Cray Research LLC
Application granted granted Critical
Publication of DE3587910D1 publication Critical patent/DE3587910D1/de
Publication of DE3587910T2 publication Critical patent/DE3587910T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
DE3587910T 1984-06-21 1985-05-13 Peripheres Interface-System. Expired - Fee Related DE3587910T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62278684A 1984-06-21 1984-06-21

Publications (2)

Publication Number Publication Date
DE3587910D1 true DE3587910D1 (de) 1994-09-29
DE3587910T2 DE3587910T2 (de) 1994-12-15

Family

ID=24495517

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3587910T Expired - Fee Related DE3587910T2 (de) 1984-06-21 1985-05-13 Peripheres Interface-System.

Country Status (6)

Country Link
US (1) US4807121A (de)
EP (1) EP0165915B1 (de)
JP (1) JPS6113359A (de)
AT (1) ATE110479T1 (de)
CA (1) CA1228677A (de)
DE (1) DE3587910T2 (de)

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US5218689A (en) * 1988-08-16 1993-06-08 Cray Research, Inc. Single disk emulation interface for an array of asynchronously operating disk drives
WO1990003031A1 (fr) 1988-09-05 1990-03-22 Seiko Epson Corporation Dispositif d'enregistrement/reproduction
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
WO1990006550A1 (en) * 1988-12-08 1990-06-14 Cray Research, Inc. Single disk emulation for asynchronous disk array
DE68929288T2 (de) * 1988-12-19 2001-11-15 Nec Corp., Tokio/Tokyo Datenübertragungsvorrichtung
DE58908047D1 (de) * 1989-04-25 1994-08-18 Siemens Ag Verfahren zur Synchronisation von Datenverarbeitungsanlagen.
US5347637A (en) * 1989-08-08 1994-09-13 Cray Research, Inc. Modular input/output system for supercomputers
US5303349A (en) * 1990-06-06 1994-04-12 Valitek, Inc. Interface for establishing a number of consecutive time frames of bidirectional command and data block communication between a Host's standard parallel port and a peripheral device
US5255372A (en) * 1990-08-31 1993-10-19 International Business Machines Corporation Apparatus for efficiently interconnecing channels of a multiprocessor system multiplexed via channel adapters
US5206952A (en) * 1990-09-12 1993-04-27 Cray Research, Inc. Fault tolerant networking architecture
US5276900A (en) * 1990-12-14 1994-01-04 Stream Computers Master connected to common bus providing synchronous, contiguous time periods having an instruction followed by data from different time period not immediately contiguous thereto
US5276684A (en) * 1991-07-22 1994-01-04 International Business Machines Corporation High performance I/O processor
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US5388217A (en) * 1991-12-13 1995-02-07 Cray Research, Inc. Distributing system for multi-processor input and output using channel adapters
JPH07122865B2 (ja) * 1992-01-02 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション バス動作の動作速度を制御するようにしたバス・インターフェースを有するコンピュータ・システム
US5640596A (en) * 1992-03-10 1997-06-17 Hitachi, Ltd. Input output control system for transferring control programs collectively as one transfer unit designated by plurality of input output requests to be executed
JP2587190B2 (ja) * 1992-09-04 1997-03-05 インターナショナル・ビジネス・マシーンズ・コーポレイション システム間チャネルページング機構
US5572691A (en) * 1993-04-21 1996-11-05 Gi Corporation Apparatus and method for providing multiple data streams from stored data using dual memory buffers
EP0641139B1 (de) * 1993-07-13 2002-09-11 Hewlett-Packard Company, A Delaware Corporation Kombinieren von Ton- und Fernsprech-Daten für einem Rechner
DE69300523T2 (de) * 1993-11-26 1996-03-14 Sgs Thomson Microelectronics Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät.
US5577213A (en) * 1994-06-03 1996-11-19 At&T Global Information Solutions Company Multi-device adapter card for computer
EP0685803B1 (de) 1994-06-03 2001-04-18 Hyundai Electronics America Herstellungsverfahren für einen elektrischen Vorrichtungs-Adapter
US5548791A (en) * 1994-07-25 1996-08-20 International Business Machines Corporation Input/output control system with plural channel paths to I/O devices
US5619731A (en) * 1994-09-23 1997-04-08 Ardent Teleproductions, Inc. Interactive music CD and data
US5495614A (en) * 1994-12-14 1996-02-27 International Business Machines Corporation Interface control process between using programs and shared hardware facilities
US5613162A (en) * 1995-01-04 1997-03-18 Ast Research, Inc. Method and apparatus for performing efficient direct memory access data transfers
EP0732659B1 (de) * 1995-03-17 2001-08-08 LSI Logic Corporation (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung
US5864712A (en) * 1995-03-17 1999-01-26 Lsi Logic Corporation Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable environment
JP3518034B2 (ja) * 1995-03-30 2004-04-12 三菱電機株式会社 ソート方法並びにソート処理装置並びにデータ処理装置
WO1997006490A1 (en) * 1995-08-09 1997-02-20 Cirrus Logic, Inc. Parasitic personal computer interface
US5768624A (en) * 1996-02-28 1998-06-16 Opti Inc. Method and apparatus for employing ping-pong buffering with one level deep buffers for fast DRAM access
US6038621A (en) * 1996-11-04 2000-03-14 Hewlett-Packard Company Dynamic peripheral control of I/O buffers in peripherals with modular I/O
US6078968A (en) * 1997-10-03 2000-06-20 Vicom Systems, Inc. Platform-independent communications protocol supporting communications between a processor and subsystem controller based on identifying information
US6453394B2 (en) * 1997-10-03 2002-09-17 Matsushita Electric Industrial Co., Ltd. Memory interface device and memory address generation device
US6694381B1 (en) 1997-12-17 2004-02-17 Vicom Systems, Inc. Platform-independent communications protocol supporting communications between a processor and subsystem controller
DE19830625B4 (de) * 1998-07-09 2008-04-03 Robert Bosch Gmbh Digitale Schnittstelleneinheit
GB2362777B (en) * 2000-05-25 2002-05-08 3Com Corp System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate
US6874043B2 (en) * 2000-10-17 2005-03-29 Bridgeworks Ltd. Data buffer
GB2372115A (en) * 2001-02-08 2002-08-14 Mitel Semiconductor Ltd Direct memory access controller
US6779055B2 (en) 2001-06-20 2004-08-17 Freescale Semiconductor, Inc. First-in, first-out memory system having both simultaneous and alternating data access and method thereof
JP2003338200A (ja) * 2002-05-17 2003-11-28 Mitsubishi Electric Corp 半導体集積回路装置
US20050182863A1 (en) * 2004-02-18 2005-08-18 Arm Limited, Direct memory access control
CN101809934B (zh) * 2007-06-19 2014-07-02 北卡罗来纳科姆斯科普公司 用于使用管理端口电路的方法、系统和计算机程序产品
CN103984659B (zh) * 2014-05-15 2017-07-21 华为技术有限公司 分时使用串口的方法和装置

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US3319230A (en) * 1956-09-26 1967-05-09 Ibm Data processing machine including program interrupt feature
US3812475A (en) * 1957-12-26 1974-05-21 Ibm Data synchronizer
US3336582A (en) * 1964-09-01 1967-08-15 Ibm Interlocked communication system
US3427592A (en) * 1964-11-12 1969-02-11 Ibm Data processing system
US3400372A (en) * 1965-02-16 1968-09-03 Ibm Terminal for a multi-data processing system
US3432813A (en) * 1966-04-19 1969-03-11 Ibm Apparatus for control of a plurality of peripheral devices
US3564502A (en) * 1968-01-15 1971-02-16 Ibm Channel position signaling method and means
US3582906A (en) * 1969-06-27 1971-06-01 Ibm High-speed dc interlocked communication system interface
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
US3688274A (en) * 1970-12-23 1972-08-29 Ibm Command retry control by peripheral devices
US3725864A (en) * 1971-03-03 1973-04-03 Ibm Input/output control
US3812473A (en) * 1972-11-24 1974-05-21 Ibm Storage system with conflict-free multiple simultaneous access
FR2260141A1 (en) * 1974-02-01 1975-08-29 Honeywell Bull Soc Ind Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory
US4313160A (en) * 1976-08-17 1982-01-26 Computer Automation, Inc. Distributed input/output controller system
US4115854A (en) * 1977-03-28 1978-09-19 International Business Machines Corporation Channel bus controller
US4300193A (en) * 1979-01-31 1981-11-10 Honeywell Information Systems Inc. Data processing system having data multiplex control apparatus
US4442504A (en) * 1981-03-09 1984-04-10 Allen-Bradley Company Modular programmable controller
US4495564A (en) * 1981-08-10 1985-01-22 International Business Machines Corporation Multi sub-channel adapter with single status/address register
US4460959A (en) * 1981-09-16 1984-07-17 Honeywell Information Systems Inc. Logic control system including cache memory for CPU-memory transfers
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus

Also Published As

Publication number Publication date
EP0165915A2 (de) 1985-12-27
DE3587910T2 (de) 1994-12-15
EP0165915B1 (de) 1994-08-24
US4807121A (en) 1989-02-21
EP0165915A3 (en) 1988-12-07
JPS6113359A (ja) 1986-01-21
CA1228677A (en) 1987-10-27
JPH0562382B2 (de) 1993-09-08
ATE110479T1 (de) 1994-09-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee