DE3583593D1 - Speicherhierarchie und deren betriebsverfahren. - Google Patents

Speicherhierarchie und deren betriebsverfahren.

Info

Publication number
DE3583593D1
DE3583593D1 DE8585112902T DE3583593T DE3583593D1 DE 3583593 D1 DE3583593 D1 DE 3583593D1 DE 8585112902 T DE8585112902 T DE 8585112902T DE 3583593 T DE3583593 T DE 3583593T DE 3583593 D1 DE3583593 D1 DE 3583593D1
Authority
DE
Germany
Prior art keywords
operating procedure
storage hierarchy
hierarchy
storage
procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585112902T
Other languages
English (en)
Inventor
James Herbert Pomerene
Thomas Roberts Puzak
Rudolph Nathan Rechtschaffen
Kimming So
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3583593D1 publication Critical patent/DE3583593D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8585112902T 1984-12-24 1985-10-11 Speicherhierarchie und deren betriebsverfahren. Expired - Fee Related DE3583593D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/685,527 US4774654A (en) 1984-12-24 1984-12-24 Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory

Publications (1)

Publication Number Publication Date
DE3583593D1 true DE3583593D1 (de) 1991-08-29

Family

ID=24752584

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585112902T Expired - Fee Related DE3583593D1 (de) 1984-12-24 1985-10-11 Speicherhierarchie und deren betriebsverfahren.

Country Status (5)

Country Link
US (1) US4774654A (de)
EP (1) EP0185867B1 (de)
JP (1) JPS61156346A (de)
CA (1) CA1238984A (de)
DE (1) DE3583593D1 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
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JPS62194563A (ja) * 1986-02-21 1987-08-27 Hitachi Ltd バツフア記憶装置
FR2609195A1 (fr) * 1986-12-31 1988-07-01 Thomson Csf Procede de gestion d'antememoires associees a des processeurs dans une architecture multiprocesseur a bus unique et systeme de traitement de donnees fonctionnant suivant ce procede
US4980823A (en) * 1987-06-22 1990-12-25 International Business Machines Corporation Sequential prefetching with deconfirmation
US5113511A (en) * 1989-06-02 1992-05-12 Atari Corporation System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions
US5155832A (en) * 1989-07-05 1992-10-13 Hewlett-Packard Company Method to increase performance in a multi-level cache system by the use of forced cache misses
US5125085A (en) * 1989-09-01 1992-06-23 Bull Hn Information Systems Inc. Least recently used replacement level generating apparatus and method
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5203002A (en) * 1989-12-27 1993-04-13 Wetzel Glen F System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle
US5467460A (en) * 1990-02-14 1995-11-14 Intel Corporation M&A for minimizing data transfer to main memory from a writeback cache during a cache miss
EP0461926B1 (de) * 1990-06-15 1998-09-02 Compaq Computer Corporation Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien
US5392417A (en) * 1991-06-05 1995-02-21 Intel Corporation Processor cycle tracking in a controller for two-way set associative cache
US6453388B1 (en) 1992-06-17 2002-09-17 Intel Corporation Computer system having a bus interface unit for prefetching data from system memory
US5787475A (en) * 1992-07-21 1998-07-28 Digital Equipment Corporation Controlled prefetching of data requested by a peripheral
JPH06222990A (ja) * 1992-10-16 1994-08-12 Fujitsu Ltd データ処理装置
EP0612013A1 (de) * 1993-01-21 1994-08-24 Advanced Micro Devices, Inc. Kombination von Vorausholungspuffer und Befehlscachespeicher
US5539914A (en) * 1993-06-14 1996-07-23 International Business Machines Corporation Method and system for preprocessing data block headers during access of data in a data storage system
US5809525A (en) * 1993-09-17 1998-09-15 International Business Machines Corporation Multi-level computer cache system providing plural cache controllers associated with memory address ranges and having cache directories
US5530832A (en) * 1993-10-14 1996-06-25 International Business Machines Corporation System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
US5721854A (en) * 1993-11-02 1998-02-24 International Business Machines Corporation Method and apparatus for dynamic conversion of computer instructions
US5603004A (en) * 1994-02-14 1997-02-11 Hewlett-Packard Company Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
US5539895A (en) * 1994-05-12 1996-07-23 International Business Machines Corporation Hierarchical computer cache system
US5577227A (en) * 1994-08-04 1996-11-19 Finnell; James S. Method for decreasing penalty resulting from a cache miss in multi-level cache system
US5860096A (en) * 1994-10-17 1999-01-12 Hewlett-Packard Company Multi-level instruction cache for a computer
US5734731A (en) * 1994-11-29 1998-03-31 Marx; Elliot S. Real time audio mixer
US5790823A (en) * 1995-07-13 1998-08-04 International Business Machines Corporation Operand prefetch table
US5758119A (en) * 1995-08-23 1998-05-26 International Business Machines Corp. System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache
US5740399A (en) * 1995-08-23 1998-04-14 International Business Machines Corporation Modified L1/L2 cache inclusion for aggressive prefetch
US5787466A (en) * 1996-05-01 1998-07-28 Sun Microsystems, Inc. Multi-tier cache and method for implementing such a system
US5802563A (en) * 1996-07-01 1998-09-01 Sun Microsystems, Inc. Efficient storage of data in computer system with multiple cache levels
US6065097A (en) * 1996-08-29 2000-05-16 Sun Microsystems, Inc. Apparatus and method for sharing a unified memory bus between external cache memory and primary memory
US5937429A (en) * 1997-04-21 1999-08-10 International Business Machines Corporation Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator
US6535961B2 (en) * 1997-11-21 2003-03-18 Intel Corporation Spatial footprint prediction
US6457105B1 (en) * 1999-01-15 2002-09-24 Hewlett-Packard Company System and method for managing data in an asynchronous I/O cache memory
US6823430B2 (en) * 2002-10-10 2004-11-23 International Business Machines Corporation Directoryless L0 cache for stall reduction
US7380047B2 (en) * 2004-09-30 2008-05-27 International Business Machines Corporation Apparatus and method for filtering unused sub-blocks in cache memories
US7313656B1 (en) * 2004-12-27 2007-12-25 Emc Corporation Pre-fetch prediction method for disk drives
US8046538B1 (en) * 2005-08-04 2011-10-25 Oracle America, Inc. Method and mechanism for cache compaction and bandwidth reduction
US9559889B1 (en) * 2012-10-31 2017-01-31 Amazon Technologies, Inc. Cache population optimization for storage gateways
US9501796B2 (en) 2013-09-18 2016-11-22 Chicago Mercantile Exchange Inc. Dataset intersection determination
US20160323351A1 (en) * 2015-04-29 2016-11-03 Box, Inc. Low latency and low defect media file transcoding using optimized storage, retrieval, partitioning, and delivery techniques
KR102653852B1 (ko) * 2019-05-07 2024-04-02 에스케이하이닉스 주식회사 컨트롤러, 메모리 시스템 및 그것의 동작 방법
EP3695328A4 (de) 2019-09-12 2020-12-09 Alibaba Group Holding Limited Protokollstrukturierte speichersysteme
WO2019228575A2 (en) * 2019-09-12 2019-12-05 Alibaba Group Holding Limited Log-structured storage systems
EP3673376B1 (de) 2019-09-12 2022-11-30 Advanced New Technologies Co., Ltd. Protokollstrukturierte speichersysteme
WO2019228569A2 (en) 2019-09-12 2019-12-05 Alibaba Group Holding Limited Log-structured storage systems
EP3669263B1 (de) * 2019-09-12 2022-03-02 Advanced New Technologies Co., Ltd. Protokollstrukturierte speichersysteme
CN111837101A (zh) 2019-09-12 2020-10-27 创新先进技术有限公司 日志结构存储系统
US10942852B1 (en) 2019-09-12 2021-03-09 Advanced New Technologies Co., Ltd. Log-structured storage systems
EP3682344A4 (de) 2019-09-12 2020-12-02 Advanced New Technologies Co., Ltd. Protokollstrukturierte speichersysteme
SG11202002364TA (en) 2019-09-12 2020-04-29 Alibaba Group Holding Ltd Log-structured storage systems

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3928857A (en) * 1973-08-30 1975-12-23 Ibm Instruction fetch apparatus with combined look-ahead and look-behind capability
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
US4437155A (en) * 1980-11-14 1984-03-13 Sperry Corporation Cache/disk subsystem with dual aging of cache entries
US4490782A (en) * 1981-06-05 1984-12-25 International Business Machines Corporation I/O Storage controller cache system with prefetch determined by requested record's position within data block
US4464712A (en) * 1981-07-06 1984-08-07 International Business Machines Corporation Second level cache replacement method and apparatus
US4533995A (en) * 1981-08-03 1985-08-06 International Business Machines Corporation Method and system for handling sequential data in a hierarchical store
JPS5971183A (ja) * 1982-10-15 1984-04-21 Hitachi Ltd 記憶制御方式
JPS59180877A (ja) * 1983-03-31 1984-10-15 Fanuc Ltd メモリの読出し制御方式

Also Published As

Publication number Publication date
EP0185867A3 (en) 1988-08-17
US4774654A (en) 1988-09-27
EP0185867B1 (de) 1991-07-24
EP0185867A2 (de) 1986-07-02
JPH0364893B2 (de) 1991-10-08
CA1238984A (en) 1988-07-05
JPS61156346A (ja) 1986-07-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee