DE3533629A1 - Gate-array - Google Patents

Gate-array

Info

Publication number
DE3533629A1
DE3533629A1 DE19853533629 DE3533629A DE3533629A1 DE 3533629 A1 DE3533629 A1 DE 3533629A1 DE 19853533629 DE19853533629 DE 19853533629 DE 3533629 A DE3533629 A DE 3533629A DE 3533629 A1 DE3533629 A1 DE 3533629A1
Authority
DE
Germany
Prior art keywords
connection
connection points
grid
gate array
points
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19853533629
Other languages
German (de)
English (en)
Other versions
DE3533629C2 (https=
Inventor
Axel Steigert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE19853533629 priority Critical patent/DE3533629A1/de
Publication of DE3533629A1 publication Critical patent/DE3533629A1/de
Application granted granted Critical
Publication of DE3533629C2 publication Critical patent/DE3533629C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
DE19853533629 1985-09-20 1985-09-20 Gate-array Granted DE3533629A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19853533629 DE3533629A1 (de) 1985-09-20 1985-09-20 Gate-array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19853533629 DE3533629A1 (de) 1985-09-20 1985-09-20 Gate-array

Publications (2)

Publication Number Publication Date
DE3533629A1 true DE3533629A1 (de) 1987-04-02
DE3533629C2 DE3533629C2 (https=) 1989-08-24

Family

ID=6281524

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853533629 Granted DE3533629A1 (de) 1985-09-20 1985-09-20 Gate-array

Country Status (1)

Country Link
DE (1) DE3533629A1 (https=)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3702025A (en) * 1969-05-12 1972-11-07 Honeywell Inc Discretionary interconnection process

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3702025A (en) * 1969-05-12 1972-11-07 Honeywell Inc Discretionary interconnection process

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Kroeger, J.H. und Tozun, O.N.: CAD pits semicustom chips against standard slices. In: Electronics, 3. Juli 1980, S. 119-123 *
Skokan, Z.E.: Programmable Logie Machine (A Programmable Cell Array). In: IEEE Journal of Solid-State Circuits, Bd. Sc-18, Nr. 5, Okt.1983, S. 572-578 *
Wu, Wei-Wha: Automated welding customizes programmable logic arrays. In: Electronics, H. 17, 14. Juli 1982, S. 159-162 *

Also Published As

Publication number Publication date
DE3533629C2 (https=) 1989-08-24

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee