DE3525174A1 - Transmitter circuit for generating frequency-modulated signals - Google Patents

Abstract

A transmitter circuit for generating frequency-modulated signals is described. In order to render the carrier frequency of the transmitter signal adjustable, either continuously and/or in steps, and to render variable the clock rate of the modulation signal which is to be transmitted, the transmitter circuit has a modulator circuit (1) to whose input the modulation signal (UE) is applied and in which an output signal with the shape <IMAGE> or <IMAGE> can be tapped in each case on two outputs, WH being a randomly selectable auxiliary circuit frequency of the modulator circuit which defines the modulation index, UE(t) being the modulation signal, <IMAGE> being randomly selectable, constant phase angles, <IMAGE> where n = ...0,+/-1,+/-2,+/-3, etc., by a ... to each output of the modulator circuit (1) ... Original abstract incomplete. <IMAGE>

Description

The invention relates to a transmitter circuit for generating

frequency modulated signals.

For the transmission of several signals, especially digital signals, Frequency division multiplex systems are preferred over a common transmission channel used. The modulation method used to transmit digital signals the frequency shift keying (FSK) is based on the fact that depending on the logic state of the to transmitted signal, keyed between (at least) two output frequencies will.

Each signal to be transmitted is made up of a transmitter circuit implemented from a modulator and a downstream filter circuit. The output signals all of these transmitter circuits are added and over the transmission channel to Transfer recipient.

Filter circuits to limit the spectrum of the output signal the individual transmitter circuits are generally necessary because of the spectrum of a frequency-modulated signal is theoretically infinitely wide, and therefore, um to prevent mutual interference of neighboring channels, are limited got to.

In known systems of this type, especially for the transmission of digital Signals is the transmission frequency of the transmitter circuit (= channel frequency) by frequency-determining Components firmly specified; the maximum clock rate of the Diaitalianaies to be transmitted cannot be increased by the operator of the transmitter switching.

This resulted in the manufacturer of such transmission systems the disadvantage that for each channel frequency and transmission speed a different Sender type should be available. In practice that meant for a typical Number of 24 channel frequencies at 50 baud and 5 different clock rates (50, 100, 200, 600 and 1200 baud) that a total of 46 different transmitter types would have to be manufactured and stocked. This was also for the user large variety of types associated with disadvantages, since a Plant the final configuration had to be determined and only afterwards was very difficult to change.

A simplification in the planning of such transmission systems resulted from the fact that so-called "frequency-neutral" transmitter circuits were constructed where the user can set the transmission frequency by moving jumpers on the finished device. The measure reduced the range of types to one type per transmission speed, regardless of the channel frequency, possible. The transmission speed itself is also with these transmitter circuits fixed, since the filter circuits only each for a certain transmission speed could be interpreted.

The change in the transmission speed is also with these devices just by replacing the entire transmitter circuit or at least part of it possible.

The object of the invention is to implement a transmitter circuit, at which the carrier frequency of the transmitter signal is continuous and / or in steps is adjustable and at which the clock rate of the modulation signal to be transmitted is variable.

In a transmitter circuit for generating frequency-modulated signals, this is achieved according to the invention by a modulator circuit at the input of which the modulation signal (UE) is applied and at which two outputs each have an output signal of the form or

can be tapped, where WH is an arbitrarily selectable, the modulation index defining auxiliary angular frequency of the modulator circuit, UE tr) the modulation signal, W are any selectable, constant phase angle, where the following applies with n = an angular frequency wK, the harmonic oscillation of one multiplier circuit having a constant phase shift compared to the harmonic oscillation of the other multiplier circuit, and by a summing circuit in which the output of a multiplier circuit is connected to one input and the frequency-modulated transmitter signal (UA ) is present.

The frequency wK of the harmonic oscillations with which the output signals (UA1, UA2) of the modulator circuit (1) linked in the multiplier circuits (4,5) indicates the carrier frequency of the generated frequency-modulated signal.

An embodiment of the invention can therefore consist in that each multiplier circuit comprises an oscillation generator which is a harmonic Oscillation with the angular frequency wK generated.

Another embodiment of the invention can consist in that the second input (so1, SM2) is brought out at each multiplier circuit is, and that at each of these inputs an externally generated harmonic oscillation is applied with the angular frequency wK. This can be done in a particularly simple manner a variation of the carrier frequency can be achieved.

The modulation index of the generated frequency-modulated signal, respectively the frequency deviation for digital modulation signals is through the Auxiliary circular frequency WH of the modulator circuit is determined. A preferred embodiment of the invention can therefore consist in the modulator circuit having a control input (S1), via which the auxiliary angular frequency WH of the modulator can be controlled, whereby the modulation index is adjustable, and thus arbitrary within wide limits transmission speeds possible with a transmitter circuit according to the invention are.

Below is the invention with reference to the drawings for example described. They show: FIG. 1 the block diagram of an inventive Transmitter circuit; Figure 2aa-2ac line diagrams of the output signals of the modulator circuit a transmitter circuit according to FIG. 1; Figure 3 shows a possible embodiment of an inventive Modulator circuit in analog technology; Figure 4 line diagrams of the input and output signals a circuit according to FIG. 3; Figure 5a, b digital implementations of an inventive Modulator circuit and FIG. 6 shows the time required for two internal signals and the output signals a circuit according to Fig. 5a.

1 shows the block diagram of a transmitter circuit according to the invention for generating a frequency-modulated transmitter signal.

The signal to be transmitted UE is at an input E of a modulator circuit 1, which generates two output signals UAl and UA2. About another Input S, the modulator circuit, the frequency deviation of the in the transmitter circuit generated frequency-modulated transmitter signal can be adjusted.

The control input S1 can be omitted if the frequency deviation of the Transmission signal does not have to be changeable.

each output 1 or A2 of the modulator circuit 1 is in each case via one Filter circuit 2 or 3 is fed to the input of a multiplier circuit 4 or 5, respectively. The similar low-pass filter circuits 2, 3 serve to limit the spectrum of the frequency-modulated signal and are i.a. only necessary to regulations of the To meet telecommunications authorities; come such regulations regarding the maximum spectral width of the transmission signal not applicable, or when the input signal If if certain criteria are met, the filter circuits 2, 3 can be omitted.

In the multiplier circuit 4 or 5, the product of the respective Input signal of the multiplier circuit and one each to that of the other multiplier circuit phase-shifted, but equal-frequency harmonic oscillation formed the each 1 ige product signal is present at the output AMa or AMz. The harmonic one Vibration can either be generated in the multiplier circuit 4 or 5 itself the frequency the oscillation can be adjusted, or it can be external in a common, in turn generated controllable generator and via a downstream phase splitter circuit via the control input SM1 or SM2 to the multiplier circuit 4 and 5, respectively be.

The two outputs AM1, AM2 of the multiplier circuits 4,5 are to the inputs of a summing circuit 6 and there to the output signal of the Transmitter circuit UA additively linked, which is connected to output A of the summing circuit 6 is present.

In the following, the overall function of the transmitter circuits will be discussed first can be described with the aid of the block diagram in FIG.

The input signal UE should generally be given by the time function UE (t) be described. For the transmission of digital Signals can the input function UE, assumed with UE = 1 or UE = -1, depending on the logic state will.

Two output signals are generated in the modulator circuit, to obey.

WH is an arbitrarily selectable, constant auxiliary circuit frequency, which the modulation index X of the frequency-modulated signal, or. in case of digital input signals UE, indicating the frequency deviation of the generated FSK signal.

The two phase angles 1 82 can in principle be freely selected as long as they do not differ from one another by integer multiples of. Simplifying the two phase angles with # 1 = 0 and # = # / 2 are used for the following description accepted.

This is how the output signals of the modulator circuit are calculated If the influence of the low-pass filter circuit 2, 3 is neglected for the following consideration, then these signals are present at the inputs of the multiplier circuit 3, 4. The signals UAM1 and UAg2 are emitted at their outputs.

The Ausaanassianal of the adder 6 is thus: In the above equation, UE can have any desired dependence on t. The constant logic states UE = + 1 and UE = -1, which preferably occur in the circuit according to the invention, are used below.

With UE = + 1 for t greater than to, UA (t) = sin [(wk + wH) .t + # o] With UE = l for t greater to, UA (t) = sin [(wK-wH) .t + # o] Using the above equations, is recognize that the output voltage UA is a frequency-modulated signal acts. The center frequency of the signal (= channel frequency) is determined by the frequency the harmonic oscillation used in the multiplier 4 or 5 with the, if applicable The variable angular frequency wK is determined via the control inputs S1, 5M2. The symmetrical one Frequency deviation is determined by the one used in the modulator and, if necessary, by the control input S1 variable angular frequency wH is determined. In the modulator is determined by the input voltage UE = + / - 1 the frequency deviation generated around the center frequency wK = 0. With this switchover between + wH and -wH arise in the signal curve of the output signals U, and UA2 des Modulator discontinuities but no jumps.

To the processes in the modulator 1 and the entire transmitter circuit better To make it understandable, the line diagrams of the output signals are shown in FIGS. 2aa to 2ac UA1 and UA2 of the modulator circuit for the switching times #, 7 # / 4 and 5 # / 4 shown.

According to the phase position after these switching times from UE = + 1 on UE = -1, the equation given above results in the following in each case Output voltage: Example 1 (Fig. 2aa): UE from +1 to -1 according to for UE = +1: UA (t) = sinwKt.coswHt + coswKt.sinwHt = sin (wK + wH) t for UE = -1: UA (t) = sinwKt.coswHt-coswKt.sinwHt = sin (wK-w4) t Example 2 (Fig. 2ab): UE from +1 to -1 after 7 # / 4 for UE = +1: UA (t) = sinwKt .coswHt + coswKt. sinwHt = sin (wK + wH) t for UE = -1: UA (t) = - coswKt.coswHt-sinwKt.sinwHt = -cos (wK-wo) t example 3 (Fig. 2ac): UE from +1 to -1 to 5 # / 4 for UE = +1: UA (t) = sinwKt.coswHt + coswKt.sinwHt = sin (wK + wH) t for UE = -1: = sinwKt.sinwHt + coswKt.coswHt = cos (wk-wH) t Es it should be stated here that the transmitter circuit according to the invention is not based on modulator circuits is limited, whose output signals UA1 and UA2 are 90 ° phase shift to each other exhibit; also deviating from 90 °, however. constant phase shifts of the both signals are possible. Likewise, the phase difference of the harmonic oscillations is with which the Signals UAl and U in the modulator circuits 4 or 5 linked-A2 are not restricted to the value 900. This value leads however, to a particularly clear mathematical description of the function the transmitter circuit according to the invention.

3 shows the detailed block diagram of an exemplary Realization of a modulator circuit using analog technology.

The input signal UE is applied to the integration input of an integrator 7 and fed to a sign input of a comparator 8. At two other entrances of the comparator there are two fixed values UK and Ux which are the limits of the integration range of the integrator. The output of the integrator is connected to the comparison input of the comparator, the output of the comparator is connected to the reset input of the integrator. The inputs are also at the output of the integrator two function generators 9, 10 connected, the outputs of which are the output signals Deliver UAl and UA2.

4a shows a typical time curve of a digital input signal UE; FIG. 4b shows the output signal U1 of the integrator 7 and FIG. 4c or FIG. 4d represent the corresponding output signals of the function generators 9, 10.

The basic function is described below with reference to FIG. 3 and FIG of the modulator: The input signal UE (input data) is sent to the integrator 7 and supplied to the comparator 8 as a sign recognition signal.

The direction of integration is determined by the sign of the input voltage set. The limits for the output voltage of the integrator are determined by the Voltages UK + and UK that are firmly applied to the comparator are specified. With positive input voltage UE is integrated before UK + to UK, with negative input voltage from UK to UK + integrated (Fig. 4a, b).

The input voltage UE, the time constant of the integrator and the The boundaries of the integration area UK + and # UK are coordinated so that the desired Period of 28 / wH of the sawtooth voltage UI emitted by the integrator is reached will.

The periodic sawtooth voltage UI is preferably two function generators fed, which converts the periodic sawtooth voltage UI into periodic output voltages Convert UA1, UA2 with the same period as UI and UA2 is out of phase. Preferably, as shown in Fig.4c and Fig.4d, the voltage UI in one Function generator 9 (10) in a sinusoidal voltage UAl and in another function generator 10 (9) converted into a cosine voltage UA2.

The Fig.Sa shows an example implementation of a modulator circuit in digital technology.

The (digital) input signal UE is sent to the counting direction input an up-down counter 11 applied; there is a at the clock input of the counter Clock signal S1, which is either generated in an internal clock generator 12, or generated externally and fed via the control input S1.

The parallel output lines of the counter 11 form the data bus B1 which is applied to the address inputs of a first analog multiplexer 13 and above an adding circuit 15 to the address inputs of a second analog multiplexer 14 is led.

In the adding circuit 15, the respective digital word on the Bus B1 a fixed value which is generated by the coding switch 18 and to the second Inputs of the adding circuit 15 is present, added.

Each of the analog inputs of a multiplexer is connected to the corresponding one Input of the other multiplexer connected in pairs and to a tap of a Resistance voltage divider chain 17 out, which from a voltage source 16 is fed.

In the following, the function of the Modulator described in digital form.

The counter 11 counts depending on the polarity of the input voltage UE upwards or downwards and thus fulfills the function of an integrator. The integration time constant can be set with the clock frequency of the clock generator 12.

By overflowing the counter after the period 2t w becomes A quasi-sawtooth function is achieved in a simple manner on the data bus B1, because after the binary number IIII the counter starts counting again with the binary number 0000. Functionally, the signal sequence on the data bus B1 corresponds to the signal U1 in FIG. 4b.

The data bus signal B 1 is on the one hand a 2-multiplexer 13 and on the other hand an adder 15 is supplied. The multiplexer 13 converts this signal into a known one Convert into a periodic output voltage UAl, which is preferably a sinusoidal voltage is formed with the period wt wH.

In order to have a phase shifted to UAl at the output of the second multiplexer 14 To achieve voltage UA2, is at the input of the multiplexer 14 via the data bus B2 entered a numerical value that differs from the numerical value of the data bus B1 by that Value differs, cer causes the desired phase shift. In simple This is achieved by adding that to the value in B1 with the adder 15 desired number is added, which is given by the coding switch 18.

In Figure 6 it is shown how the data bus signals B1 and B2 the quasi-sine voltage at UAl or the quasi-cosine voltage is formed in a step shape at UA2. It can also be seen that the phase shift between UA1 and UA2 a numerical value difference of binary 0100 between B1 and B2 is equivalent to.

It is also shown in FIG. 6 in a manner similar to that in FIGS. 4c and 4d the Output voltage UAl and UA2 run if the input signal is at time 2tL WH UE of +1. changes to -1.

2 # Until the time - the counter 11 counts upwards direction wH and A quasi sine voltage arises at the output UA1. From the time 2 # point wH counts the counter 11 in the downward direction and a quasi - minus - sinusoidal voltage is created at the UA.

The circuit shown in Figure 5a is only an example.

The same principle can also be solved differently in digital technology. For example, instead of the two multiplexers 13 and 14, digital-to-analog converters can be used in accordance with FIG GO r 21 are used, which are stored in a memory via upstream Conversion tables 18, 19 convert the data bus signal B1 into the desired output signal Form UA1 or UA2.

Last but not least, both the basic circuit according to FIG. 1 and the basic modulator circuit according to FIG. 3 as well as a digital modulator circuit according to FIG. 5 a or b as the basis used for programming a microprocessor and thus a realization the circuit arrangement according to the invention can be achieved in microprocessor technology.

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Claims (9)

Transmitter circuit for generating frequency-modulated signals. can be tapped, where WH is an arbitrarily selectable, the modulation index defining auxiliary angular frequency of the modulator circuit, UE (t) the modulation signal, t 2 are arbitrarily selectable, constant phase angle, where the following applies with n =. . .o, + / - 1, + / - 2, + / - 3 ,. etc. by one connected to each output of the modulator circuit (1) Multiplier circuit (4 or 5), which in each case the output signal (UA1 or UA2) the modulator circuit (1) with a harmonic oscillation of a circular frequency wK multiplied, the harmonic oscillation of the one multiplier circuit (4) compared to the harmonic oscillation of the other multiplier circuit (5) has a constant phase shift, and by a summing circuit (6), in which the output of a multiplier circuit (4 or 5) is connected and at its output the frequency-modulated transmitter signal (UA) is present. 2. Transmitter circuit according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the modulator circuit (1) has an integrator (7) and one, this having a comparator (8) arranged in parallel, the output (UI) of the integrator (7) the input of a first and the input of a second function generator (9. or 10) is connected, with the output of a function generator (9) the an output signal (UA1) of the modulator circuit and at the output of the other function generator (10) the other output signal (UA2) of the modulator circuit (1) is present (Fig. 3) 3. Transmitter circuit according to Claim 1, d u r c h g e n n n z e i c h n e t that the modulator circuit (1) has a clocked up-down counter (11), the modulation signal (UE) is applied to the direction changeover input, where on the output data bus (B1) of the up-down counter (11) a first analog multiplexer circuit (13) and a second analog multiplexer circuit via an adder circuit (15) (14) is connected, the analog inputs of the multiplexer circuits at different Voltages are, which are preferably obtained by taps on a voltage divider circuit (14) are implemented, and where the output signals (UA 1 or UA2) of the modulator circuit (1) can be tapped at the analog outputs of the analog multiplexer circuit (13 or 14) are (Fig.5a). 4. Transmitter circuit according to claim 1 or 3, d a d u r c h g e k e n n z e i c h n e t that the modulator circuit (1) has a clocked up-down counter (11) and that to the output data bus (B1) of the up-down counter two digital-to-analog converter circuits (20 or 21) each via one upstream Conversion circuit (18 or 19) are connected and with the analog outputs of the digital-to-analog converter circuits (20,21) the output signals (UA or UA2) the modulator circuit can be tapped (Fig.5b). 5. Transmitter circuit according to claim 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the modulator circuit (1) has a control input (S1), via which the auxiliary circular frequency wH of the modulator can be controlled. 6. Transmitter circuit according to one of claims 1 to 5, d a d u r c h it is noted that in each multiplier circuit (4 or 5) the each second input (SM1 or 5M2 # is brought out and that at each of these Inputs a harmonic oscillation with the angular frequency wK is present. 7. Transmitter circuit according to one of claims 1 to 5, d a d u r c h it is noted that each multiplier circuit (4 or 5) has an oscillation generator includes, which generates a harmonic oscillation with the angular frequency wK. 8. Transmitter circuit according to claim 1 to 7, d a d u r c h g e k e n n z e i c h n e t that between each output (UA1r UA2) of the modulator circuit (1) and the multiplier circuit (4 or 5) a low-pass filter circuit (2 or 3j is arranged. 9. Transmitter circuit according to one of claims 1 to 8, d a d u r c h it is not noted that it is implemented using microprocessor technology.