DE1280920B - Method for generating a voltage analogous to a binary-coded numerical value - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H 03k

German KL: 21 al - 36/00

Number: 1280 920

File number: P 12 80 920.0-31 (T 26197)

Filing date: May 15, 1964

Opening day: October 24, 1968

The invention relates to a method of production a voltage or a corresponding current analogous to a binary-coded numerical value Use of a frequency divider to which the output voltage of an alternating voltage generator is supplied, in which the briefly tapped in the same code on the divider, through the counting positions of the divisor given numbers are compared with the entered coded numerical value and in which a voltage curve is generated using this comparison, its integration results in the analog value corresponding to the coded numerical value entered.

A method of this type for generating the voltage corresponding to a binary-coded numerical value is known from US Pat. No. 2,907,021. In the known method, successive voltage pulses are generated which are assigned to the various powers of 2 (2 ° 2 ¹ 2 ² etc.) in that the lengths of successive pulses are proportional to successive powers. Of these voltage pulses of different lengths, those are each fed to an integrator, the associated powers of 2 of which, when added together, result in the digitally specified numerical value.

Such circuit arrangements are used, for example, to adjust the frequency of a telecommunications device to be able to adjust voltages remotely. You could do that above explained problem z. B. solve by having a voltage divider at the place where the voltage is needed with a number of taps corresponding to the possible numerical values and the angular position of a switch at the location of the setting to a second corresponding switch transmits at the point of voltage generation and readjusts this switch to the desired tap. To do this, however, it is necessary to have a large number of highly constant, individually adjustable Use resistors in the voltage divider that are constant even when the environmental influences change have to stay. In addition, such arrangements are not built using microminiature technology can be.

The known method described above has the disadvantage that no decimal-binary coded Numerical values can be converted into analog values. Especially with the possible application described above Such a method, however, makes it necessary to use decimal-binary-coded numerical values in To convert analog values. A suitable one for this

Method for generating a one
binary coded numerical value analog voltage

Applicant:
Telefunken

Patentverwertungsgesellschaft mb H.,
7900 Ulm, Elisabethenstr. 3

Named as inventor:

Dipl.-Ing. Ulrich Mester, 6200 Wiesbaden-Igstadt

Creating a method is to be regarded as the object on which the invention is based.

The inventive method is characterized in that for the purpose of generating a

ao an analog value corresponding to a decimal-binary-coded numerical value η a known decadically structured frequency divider is used, from which decimal-binary-coded numerical values can be continuously tapped, and that the voltage profile required for the integration is generated by a voltage or Power generator is switched on by an output pulse of the frequency divider and is switched off with the aid of comparison stages when the entered coded numerical value η and the numerical value that can be briefly accessed on the divider match.

The principle of the invention will be explained with reference to the simple embodiment of FIG. The number of voltage levels that can be generated should be ten here. The frequency divider 1 consists of four flip-flops la to Id. The frequency divider is fed with an alternating voltage from the generator 2, the frequency of which can be selected as desired. The frequency divider 1 reaches its end position after nine pulses and returns to its starting position after the tenth pulse. At the same time it emits a pulse at its output which, according to the invention, is used to put a voltage generator into operation. In the present example, this voltage generator is a bistable stage 3, which is tilted by the pulse of the divider 1 and at the output of which a voltage U _A now appears. The numerical value whose analog voltage is to be generated is set on element 5. This element 5 is in practice a multiple switch, of which four outputs when using the 1-2-4-8 code and, for example

809 628/152 +

to 4 c are still connected to an AND gate 8, which emits an output signal only when output signals occur simultaneously at all comparison stages and thus causes the voltage U _A to be switched off only when the positions of all three dividers match the settings of the corresponding adjustment members match. At the output of the integrating member 7, one of the settings on the three adjusting members 5 α to

a setting of a seven on the setting knob, the first output eme positive voltage, the second Output a positive voltage, the third in turn a positive voltage and finally the fourth emits a negative voltage. In the example chosen, the frequency divider 1 is from the starting position of the divider calculated after seven periods of the alternating voltage from generator 2, which is followed by a pulse shaper 6, one

Position reached in which analog voltage can be tapped at the four outputs of the io 5 c. Flip-flops of divider 1 the same combination. In the arrangements described so far,

of positive and negative voltages, as described above, the links 4 in practice from four individual ones is achieved. Since the comparison stages with two AND and one OR placed on element 5 are compared with the short-term gates, and for the necessary comparison of the number provided on one of the flip-flop outputs with the instantaneous values of the definition combinations on element 4 , lers, the complementary values of the individual, if the two numbers to be compared and the instantaneous values of the divider combinations are equal, an output signal is required at the circuit. Both values, once set number equal to 4 appears, will be with the selected and the instantaneous value and on the other hand the COM example when reaching position 7, so after so plemente to do so, are combined in the seven-and-seven pulses on the input of the divider 1, on Gates compared, and the output pulses of this output of the comparison stage 4 appear a pulse,
which is used to set the bistable stage 3 in their
to tilt another stable state. Thus, in the example chosen, after seven a 35
output pulses the output voltage U _{A of} the bi

Gates that only emit an output pulse when voltage occurs at the same time will be fed to the OR gate.

This circuit can be simplified for the following reason: As already described, the voltage at the output of the is (with a set number ti) due to the rc-th pulse

pulse repetition rate is - £ - when f _{0 made} the frequency of the bistable stage 3 to zero. Between this ^r ° ⁿ / o ° ^ 30 η-th impulse and the subsequent output

pulse of the divider, further pulses can definitely be sent to the switch-off input of the bistable Level 3 come without anything happening.

t _{n of} the impulses is t " = f, if one with η the am" ° ie entire coincidence circuit may be more / 0 35 clear, if one only makes sure that the first

Pulse that comes to the switch-off input of the bistable stage from the «th of the one fed to the divider Pulse sequence originates. Such a simplified circuit is shown in FIG. 4. The desired numbers

stable stage 3. The output voltage U _{A of} the bistable multivibrator is shown in FIG. The im-

Generator 2 is. The distance between two successive pulses is then At = ^, and the length

/ 0

Link 5 denotes set number. In the present example, t is _n -f. Thus the area is the

Pulses proportional to the number η and those by the

Integration in the element 7 obtained from this 40 are set here at the switch 9, the corresponding

voltage U _{g is} also proportional to the number n.

This direct voltage is only dependent on η and the maximum voltage of the element 3, but not on the frequency / ₀ . The task at hand is thus solved.

For the sake of simplicity, a very simple exemplary embodiment has been used to explain the invention selected, on which only ten different numbers can be set and with the correspondingly only ten span

accordingly its position puts one of the lines 13 to ground. In the marked points 11 of the matrix 10 there are diodes which become conductive when the ground is applied and which connect one of the lines 13 to one or some of the lines 14. The diodes are switched on in such a way that the set number η appears on the lines 14 through the output voltages. This is calculated with the complement of the number in divisor 1 in

voltages can be generated. The arrangement 50 and circuits 18 can be compared. At their output for generating analog voltages, however, a signal (positive voltage) also appears when both expand, e.g. B. to a thousand possible settings. Lead inputs voltage or no voltage, Such an embodiment is shown in FIG. 3. if having one of the inputs ground potential, here are three series-connected frequency at the output of the OR gate 19 changes the prime la, Ib and Ic are provided, which about the voltage state when all AND gates no off pulse shaper 6 pulses are supplied. Show output voltage at. This voltage change of the divider Ic is obtained here after a thousand tion is used to switch the element 3. Periods of the input frequency an output pulse, which, as in the example of FIG. 1 causes the output of element 3 to appear for the first time after the second pulse. 60 gears of all AND circuits de-energized; So that the divider la counts the units here, the divider Ib the - member 3 is switched over at the second pulse. Tens and the Teileric the hundreds. After the fourth pulse appears at the output of the divider there is a comparison stage 4 a, 4 δ and 4 c to-OR gate 19 again the original voltage order, which in its mode of operation is the comparison state, which in turn occurs with the sixth pulse level 4 of the F i g. 1 correspond. For the three decades ⁶ S changed. However, this change in voltage also has three adjusting members 5 a, 5 b and 5 c in front of no influence on member 3, which also corresponds to member 5 of FIG

speak. The outputs of the three comparison stages 4 α of analog voltages can also be used there for

where the desired DC voltage is a non-linear function of the set number η . Especially when it comes to the electronic coordination of telecommunications equipment, it is important to control z. B. varactor diodes necessary to generate voltages that are not proportional to the set frequency value, since it is known that the tuning voltage and the set frequency are non-linearly related. In such a task, a conversion matrix is switched on between the setting element and the comparison circuits, in which in the arrangement described up to now the set number is compared with the brief positions of the divider, at whose input the number η is set and at whose output the number / _(n; is available. This number f, _n> is then used, as before, the number η to generate the analog voltage, whereby this number must of course also be present in the same code in which the numerical values in the divider are briefly available stand. an exemplary embodiment of such arrangement is shown in F i g. 5, it being assumed here that the dependence of the desired DC voltage from the number η square is (JJ _g = n ^2). It is assumed here for simplicity that only ten values are to be converted from 0 to 9. These values can be set at switch 9. They must be converted into values 0, in the conversion matrix 10. 1, 4, 8, 16 ... 81 can be converted. In practice, diodes are located at the marked points 11 of the matrix, which become conductive when the switch 9 is in the appropriate position and which connect one of the transverse connecting lines 13 to one or more perpendicular connecting lines 14. This gives some of the circuits 15 positive potential. In the embodiment shown in FIG. 5, the line 13 a assigned to the number 5 is at the plus potential. Because the diodes are switched through, lines 14 a, 14 b and 14 c are also at positive potential. This constellation of lines 14 represents the numerical value 25 (5 ² ). The lines 14 are assigned to the respective underlying flip-flops of the divider 1. After the twenty-fifth pulse from the pulse generator 2 and 6, the same voltage ratios as on the lines 14 can be tapped on this via the lines 16. This means that all elements 15 are positive at the output in this position of the divider, because these elements 15 are designed in such a way that a positive output signal is generated if the voltages applied are equal (both voltages, positive = 1 or negative = 0). The AND gate with a negated output becomes negative if eight positive voltages are input at the same time at the output. This signal de-energizes the output of the bistable stage 3. As in the embodiment of FIG. 1, an output voltage appears at the output of the bistable stage 3 when the divider 1 sends a signal to its output, which in the present case happens at the hundredth pulse. The output voltage of the bistable stage is also integrated here in the element 7 and a DC voltage is taken off at its output, which is analogous to the number 25 in the example chosen. The voltage U _g is thus, as desired, proportional to n ² .

The steps 15 for determining the equivalence can be saved if the numbers briefly present in the divider 1 are compared with the matrix number specified by the position of the switch 9 in the matrix itself and if the numbers are equal, the bistable step 3 can be tilted back. In this case, however, the divider, switch and matrix must be grouped closely together, since switching capacitance and line lengths play a role _{depending on the frequency / 0.}

ίο If you also want to take two-digit decadic numbers into account, the effort on the conversion matrix and on the counter increases significantly (e.g. 99 ² = 9801). You need a divisor with four decades and a complicated conversion matrix.

For each additional decimal digit you need two additional counting decades to form the square and a large conversion matrix.

As already mentioned, the selected conversion should only be viewed as an example. In the same Way, simply by changing the arrangement of the diodes in the matrix, can be used for any other conversion according to the given function /, ", realized will.

As already mentioned above, the effort on the conversion matrix and on the divider increases very strongly if you want to convert multi-digit numbers and then generate voltages analogous to these converted numbers. You can now interpolate to reduce the effort if you can get by with an approximation. For this purpose, the two analog voltages of neighboring converted numbers are generated at the same time and a voltage divider is provided. B. ten intermediate values can decrease. However, a circuit that uses the similar logic stages as in the arrangement described so far is much more favorable, especially in the case of remote voting. An exemplary embodiment for this is shown in FIG. 6. In this exemplary embodiment, numbers η = 0, 10, 20, etc. to 90, which can be set on the switch 20, are converted in the conversion matrix 21 into their square numbers. This conversion matrix is constructed in such a way that when the number η is set at its one output (22 a and 22 b) the number ri = n- and at its other output (23 α and 23 b) the number n "- {n + I) - is available These numbers are compared with the numbers in the equivalent circuits 25 a and 25 b or 26 a and 26 b given by the brief positions of the two-decadic divider 24, which operates as described, whereby an output signal is produced the aND circuit 27 when each of the two multi-pole inputs of these circuits have the same input signal. if in both stages of the divider 24 reaches the position is given by n '== n, it receives on two inputs of a signal and makes the Flip back the bistable multivibrator, which corresponds to the previous stage 3, as a result of which its output voltage U _A = 0. The stage 28 is brought into the position in which the output voltage of this stage 28 begins by a signal from the divider 24 , whereby, as in the previous exemplary embodiments, this signal occurs when the divider 24 passes into the starting position. The length of the output pulse of stage 28 is thus proportional to the number n ² . Since the bistable stage 29 is tilted into the position by the signal from stage 27,

in which a voltage appears at its output, and its tilting back due to the AND circuit 30 is effected, the length of the output pulse of stage 29 is proportional to the number

The output signals of the two stages 28 and 29 are shown in FIGS. 7a and 7b, with FIG. 7 a shows the output voltage of stage 28 and FIG. 7 b shows the output voltage of stage 29. According to the development of the invention the two decade divider 24 is connected upstream of still another divider 31, which is supplied from the pulse generator 2, 6, the pulses at the pulse repetition frequency of _10/0, if the designated 24 supplied pulse repetition frequency / ₀ the divider. A setting switch 32 for the numbers 0 to 9 is also assigned to this divider 31. The number set on it is compared in stage 33 with the numbers given by the positions of divider 31, an output signal being generated at stage 33 when the divider 31 is in the position in which the two numbers correspond. The bistable stage 34 is toggled into the position in which it emits a voltage at the output 35 by every output signal of the divider 31, that is to say with every transition of the divider 31 to the starting position. This bistable stage 34 is tilted into the other position by an output pulse from stage 33. The voltage curve shown in FIG. 3 <> FIG. 7c thus arises at the output of stage 34, the width of the pulses being proportional to the number set on the setting switch. The outputs of the stages 29 and 34 are fed to an AND circuit 36, at the output of which the voltage profile shown in FIG. 7d is obtained. The length of the sections from the pulse sequence of FIG. 7c corresponds to the length of the pulses from FIG. 7b, ie the length of the sections is proportional to the number

The outputs of stage 36 and stage 28 are fed to an OR gate 37, which results in the voltage profile shown in FIG. 7e. This voltage curve is integrated in link 38. The voltage obtained at the output of this element is analogous to a number between n ² and (ra + 1) ² , the distance to the number n ^{2 being given} by the number set on switch 32. When setting z. B. the number 5 at the switch 32, the voltage at the output of the integrator 38 is analogous to the number lying in the middle between the numbers n ² and (n + 1) ² , that is, the same

With this type of digital-to-analog conversion, the DC voltage only needs to be applied at a single point be constant. Their allocation to the desired value is done with digital logic circuits, which allow extensive miniaturization in integrated circuit technology.

In addition, the setting can be easily controlled remotely and can be used in any binary code can be made at unlimited distances.

According to the last-described method with linear interpolation, any curves Ug = / _{n) can be represented by dividing the curve by coarse points and performing the linear interpolation in between.

If great accuracy is required, the abscissa over which the curve is plotted can be used is, for the desired curve area instead of ten z. B. divide into hundred parts and intermediate values restore by linear interpolation.

Claims (4)

Patent claims: 1. A method for generating a binary-coded numerical value analog voltage or a corresponding current using a frequency divider to which the output voltage of an alternating voltage generator is fed, in which the numbers given by the counting positions of the divider can be briefly tapped in the same code on the divider input coded numerical value are compared and in which a voltage curve is generated using this comparison, the integration of which results in the analog value corresponding to the input coded numerical value, characterized in that for the purpose of generating a decimal-binary-coded numerical value η corresponding to an analog value known decadic frequency divider is used on which continuously decimal-binary-coded numerical values can be tapped, and that the voltage curve required for the integration is generated by a voltage or current generator from an output The pulse of the frequency divider is switched on and, if the coded numerical value entered matches the numerical value that can be briefly accessed on the divider, it is switched off with the aid of comparison stages. 2. The method according to claim 1, characterized in that in a manner known per se with the help of a conversion matrix, a decimal-binary-coded number m is converted into another decimal-binary-coded number η which is linked to the first number via a specific function η = / _{( m)} , and that the number η generated in the conversion matrix is used for comparison with the counting positions of the divider. 3. The method according to claim 2, characterized in that for the purpose of linear Interpolation between two neighboring analog voltage values both voltage values generated and applied to the ends of a multi-stage voltage divider, at its taps the interpolated voltage values are tapped. 4. The method according to claim 2, characterized in that for the purpose of linear interpolation both a voltage curve, the integration of which is the analog value to the number W ₁ = / _(mi ) - results, as well as a voltage curve, the integration of which equals the analog value to the difference results, it is generated that by means of a further divider stage upstream of the divider and of Comparison stages and a voltage generator a pulse train is generated whose pulse train frequencies 10 ^a times as large as the pulse train frequency of the pulse train fed to the integrator (a = number of decadic divider stages) and whose pulse width is proportional to the number set for the interpolation that a section 10 is cut out, the length of which corresponds to the difference d, and that this section is fed to the integrator in addition to the voltage curve corresponding to the number H ₁ = / (",). Considered publications:
U.S. Patent No. 2,907,021. For this purpose 2 sheets of drawings