GB1047676A - Improvements in or relating to data processing circuits - Google Patents

Abstract

1,047,676. Interpolation devices. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. May 13, 1965 [May 15, 1964], No. 20308/65. Heading G4H. A number stored in coded binary form is compared in a comparator 4 (Fig. 1, not shown) with the output from a counter 1 into which clock pulses are fed, a bi-stable device 3 being set to one of its stable states when the inputs to the comparator are identical so that there is no output from it and it is returned to its other state when the counter 1 reaches its maximum count. The output pulses from the bi-stable device, the length of which depends on the original number stored, are passed to an integrator 7 which produces a D.C. voltage proportional to the stored number. The apparatus may be adapted for numbers of up to 1000 by using three counters A1, B1, C1 (Fig. 3, not shown), the outputs from which are compared with the units, tens, and hundreds of the stored number, an AND gate A only being actuated to change the state of a bi-stable device 3 when there are inputs from all the comparators A4, B4, C4. The apparatus may be used to get a D.C. voltage corresponding to a number n<2> when a number n is indicated on a distributer switch 9 (Fig. 5, not shown) by connecting diodes 11 at selected cross-points of the conductors 13, 14 so that the output on the wires 14 is the square of the number indicated by the distributer switch 9, in binary coded form. The apparatus may be used as an interpolation device. A diode matrix 21 (Fig. 6) produces, for an input n, outputs n<2> and (n+1)<2> on leads 22a, 22b and 23a, 23b. These outputs are compared at gates 27, 30 respectively with the outputs from a counter 24 and passed to bi-stable devices 28, 29. The bi-stable device 29 is inhibited by the output from gate 27 so that its output is a pulse of length proportional to (n+1)<2> - n<2>. Simultaneously, a number k (less than 10) is compared with the output of a counter 31 to switch a bi-stable device 34 (as in Fig. 1), the output of which is sent together with the output from gate 29 to an AND gate 36, the output of which is thus proportional to This together with the output of bi-stable device 28 is passed to an OR gate 37, the outputs from which is sent to an integrator 38. If for example k had been chosen to be equal to 5 the output from the integrator 38 would have been the analogue of a number halfway between n<2> and (n+1)<2>.