US3798636A - Series-shunt switching pair, particularly for synchro to digital conversion, dc or ac analog reference multiplying or plural synchro multiplexing - Google Patents

Abstract

In a multiplexing converter of synchro data to digital form, a plurality of switching devices, associated control logic, and a single analog comparator are provided for specifying the octant in which the synchro shaft angle is located. In a device, particularly for converting synchro data to digital form, for multiplying a DC or AC analog reference signal or for multiplexing plural synchro signals, a series-shunt switching pair is provided for presenting a constant impedance to a driving source in order to eliminate transients reflected back to the driving source when a variable impedance is presented to the driving source.

Description

Gordon et al.

[11] 3,798,636 Mar. 19, 1974 SERIES-SHUNT SWITCHING PAIR, PARTICULARLY FOR SYNCHRO TO DIGITAL CONVERSION, DC OR AC ANALOG REFERENCE MULTIPLYING OR PLURAL SYNCHRO MULTIPLEXING Inventors: Bernard M. Gordon, Magnolia;

Leopold Neumann, Lexington. both of Mass.

Gordon Engineering Company, Wakefield, Mass.

Filed: Apr. 23, 1971 Appl. No.: 137,016

Related US. Application Data Division of Ser. No. 823,421, May 9 1969, Pat. No. 3,611,354.

Assignee:

u;s. Cl 340/347 AD, 307/251 Int. Cl. H03k 5/20, H03k 17/00 Field of Search 340/347 DA, 347 AD;

References Cited UNITED STATES PATENTS 10/1971 Gordon et al 307/251 3,558,921 l/l9 7l Shi et al 307/251 3.582.975 6/1971 3,517.213 6/1970 Britten. Jr 307/251 Primary Examiner-Thomas A. Robinson Attorney, Agent, or Firm-Morse, Altman, Oates &

Bello [57] ABSTRACT In a multiplexing converter of synchro data to digital form, a plurality of switching devices, associated control logic, and a single analog comparator are provided for specifying the octant in which the synchro shaft angle is located. In a device, particularly for converting synchro data to digital form, for multiplying a DC or AC analog reference signal or for multiplexing plural synchro signals, a series-shunt switching pair is provided for presenting a constant impedance to a driving source in order to eliminate transients reflected back to the driving source when a variable impedance is presented to the driving source.

3 Claims, 4 Drawing Figures SOURCE |FROM SSSP 54 58 i :CON;'|ROL)LER I I l 52 FROM SSSP I CONTROLLER l l (FIG. I) L. l

l SERIES-SHUNT SWITCHING PAIR, PARTICULARLY FOR SYNCIIRO TO DIGITAL CONVERSION, DC OR AC ANALOG REFERENCE MULTIPLYING OR PLURAL SYNCI-IRO MULTIPLEXING CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a division of Ser. No. 823,421, filed May 9, 1969, now U. S. Pat. No. 3,611,354.

BACKGROUND AND SUMMARY The present invention relates to converters of synchro data to digital form and particularly to converters in which DC or AC analog reference signals are processed by successive approximation or the like. The present invention relates particularly to a series-shunt switching pair technique for use in such a data form converter. This technique involves the signal processing of trigonometric functions, in a synchro data to digital form converter, in such a way as to determine with unusual convenience the octant in which the synchro shaft angle is located. In a synchro to digital converter, synchro voltages are applied to a Scott transformation unit and are presented as sine and cosine functions of a synchro shaft angle to analog representation demodulator. Each sine and cosine function is applied to its correlative analog demodulator and is presented as a varying DC signal to an analog comparator. The combination of a pair of analog demodulators and an analog comparator is provided for determining the polarity of the sine function, the polarity of the cosine function, and their relative magnitudes. This combination is required for each input synchro. The analog comparator output signals, representing sine and cosine functions, are applied to an analog to digital converter in such a way that the greater magnitude function serves as a reference signal. Since analog demodulators have a slow response time, such converters have suffered from slow conversion speed. Furthermore, since a pair of analog demodulators and an analog comparator are required for each input synchro converters for multiplexing synchro data to digital form have been cumbersome and expensive. In a typical successive approximation converter, conversion is accomplished by switching, in a logically programmed sequence, a reference voltage with respect to a resistive divider network to provide for comparison between referenced signal increments and input data dignal increments. Such a converter has suffered from switching transients which have been re flected back to a driving source as a result of a variable impedance presented to the driving source as switching occurs. Such transients constitute conversion errors.

A primary object of the present invention is .to proanalog comparator for controlling a state of each of the aforementioned flip-flops. The combination of switching network, logic network, cosine polarity flipflop, sine polarity flip-flop, magnitude flip-flop and analog comparator is such as to provide a high speed synchro data to digital form converter, which is unusually compact and inexpensive.

Another object of the present invention is to provide, in converters and multiplexers employing switching devices, a novel series-shunt switching pair for presenting a constant impedance to the driving source during switching, whereby switching transients are avoided and conversion errors are minimized.

The invention accordingly comprises the apparatus possessing the construction, combination of elements, abd arrangements of parts that are exemplified in the following detailed disclosure, the scope of which will be indicated in the appended claims.

BRIEF DESCRIPTION OF DRAWINGS For a fuller understanding of the nature and objects of the present invention, reference should be had to the following detailed description taken in connection with the accompanying drawings wherein:

FIG. 1 is a block and schematic diagram of a synchro to digital converter embodying the present invention;

FIG. 2 is a block and schematic diagram of a multiplying AC or DC analog reference converter embodying the present invention;

FIG. 3 is a schematic diagram of a series-shunt switching pair, particularly applicable to the converters of FIGS. 1 and 2; and

FIG. 4 is an angular representation of a conversion technique, particularly applicable to the converter of FIG. 1.

DETAILED DESCRIPTION Generally, the synchro to digital system of FIG. 1 comprises a input terminal 12 for receiving a plurality of AC signals, a synchro network 14 for supplying a plurality of synchro shaft angle related signals, a Scott transformation network 16 for supplying a plurality of trigonometric signals, for example, sine and cosine signals, a constant impedance multiplex network 18 for supplying individual sine and cosine signals, an analog to digital converter 20 for converting the individual sine and cosine signals to digital form, and an output terminal 22 for presenting a digital signal representing the value of a synchro shaft angle.

In the device of FIG. 1, AC inputs from input network l2 are applied to synchros 24, 26 and 28 of synchro network 14. Stator voltages from synchros 24,26 and 28 are applied to Scott transformation networks 30, 32 and 34, respectively. Each stator voltage amplitude is a function of the shaft position of its correlative synchro. Itwill be understood that, in alternative embodiments, the signals as at-the input of the Scott transformation network are supplied by means other than the synchro network, for example, a resolver network. Scott transformation network output voltages, representing sine and cosine functions of synchro shaft position, for example, are applied to constant impedance multiplexer network 18. In the following discussion, for convenience, sine A and cosine A represent the output voltages of Scott transformation network 30, sine B and cosine B represent the output voltages of Scott transformation network 32, and sine C and cosine C represent the output voltages of Scott transformation network 34. Sine A, cosine A, sine B, cosine B, sine C and cosine C are applied to resistors 35, 37, 39, 41, 43 and 45, respectively. Resistors 35, 37, 39, 41, 43 and 45 are connected to series- shunt switching pairs 36, 38, 40, 42, 44 and 46, respectively.

A typical series-shunt switching pair, hereinafter referred to as an SSSP, is shown in FIG. 3 at 47. This SSSP represents a constant load to a driving source 48, such as a Scott transformation network. An output voltage 49 from driving source 48 generates 'a current in impedance 50, which is shown as being a resistor. A pair of field effect transistors 52 and 54 switch the current to a ground 56 or into a low impedance virtual ground at an input 60 of an operational amplifier 58. Field effect transistors 52 and 54 are shown as being controlled by an SSSP controller 66. A feedback resistor 62 across amplifier 58 reconverts the current to a voltage 64.

In FIG. 1, the outputs of SSSPs 36, 40 and 44 are applied to operational amplifier 70; and the outputs of SSSPs 38, 42, and 46 are applied to an operational amplifier 68. As previously stated, sine functions are the inputs of SSSPs 36, 40 and 44 and cosine functions are the inputs of SSSPs 38, 42 and 46. Therefore, the angular shaft positions of synchros 24, 26 and 28 are presented as sine functions at an output terminal 72 of operational amplifier 70 and as cosine functions at an output terminal 74 of operational amplifier 68. Output terminals 72 and 74 are connected to input terminal 76 and 78, respectively, of analog to digital converter 20.

. ln analog to digital converter 20, as illustrated, thirteen comparisons are required for each complete conversion. It will be understood that, in alternative embodiments, the number of comparisons is other than thirteen, for example, fifteen. The first three comparisons are used to establish in which one of eight octants, shown in FIG. 4, the synchro shaft angle is located.

TABLE .POLARITY Greater Octant Sine Cosine Magnitude No. 1 Positive Positive Cosine No. 2 Positive Positive Sine No. 3 Positive Negative Sine No. 4 Positive Negative Cosine No. Negative Negative Cosine No. 6 Negative Negative Sine No. 7 Negative Positive Sine No. 8 Negative Positive Cosine The preceeding table indicates that one octant is distinguished from any other octant by determining (a) the polarity of the cosine function, (b) the polarity of the sine function and (c) the relative magnitudes of these functions. For example, if the polarity of the sine function is positive, the polarity of the cosine function is positive and the magnitude of the cosine is greater than the magnitude of the sine, the synchro shaft angle is located in octant No. 1; if the polarity of the sine function is positive, the polarity of the cosine function is positive and the magnitude of the sine is greater than the magnitude of the cosine, the synchro shaft angle is located in octant No. 2. g

A programmer 80, a cosine polarity flip-flop 82, a sine polarity flip-flop 84, a magnitude flip-flop 86, a switch logic 88 circuit, SSSPs 90, 92, 94 and 96, and a comparator 98 serve to determine the octant wherein the synchro shaft angle is located. Cosine polarity flipflop 82 is triggered to a state ONE by a flip-flop pulse No. 1 from programmer 80. An output signal 100 from cosine flip-flop 82 is applied to switch logic circuit 88. SSSP 90 is energized to a conducting state by an output 102 from switch logic circuit 88 through a diode 87, whereby current flows through a resistor 104 to a summing bus 106 of comparator 98. When the current at 106 is negative with respect to a ground 108, a reject pulse is applied by comparator 98 to cosine polarity flip-flop 82, which is triggered to state ZERO. When the current at 106 is positive with respect to ground 108, an accept pulse is applied by comparator 98 to cosine polarity flip flop 82, which remains in state ONE. In a similar manner, a program pulse No. 2, sine polarity flip-flop 84, switch logic 88, diode 91, SSSP 92 and comparator 98 serve to determine the polarity of the sine function. Magnitude flip-flop 86 is triggered to state ONE by a program pulse No. 3 from programmer 80. An output signal 110 from the magnitude flip-flop 86 is applied to switch logic 88. SSSPs 90, 94 and 114 are energized to the conducting state by an output 112 from logic switch 88, SSSP 90 is energized by the output 112 through a diode 93. The arrangement is such that currents then flow through resistors 116 and 104 to the summing bus 106 of comparator 98. When the current at 106 is negative with respect to ground 108, a reject pulse is applied by comparator 98 to magnitude flip-flop 86 in order to reset magnitude flip-flop 86 to state ZERO. SSSPs 90 and 94 are de-energized to the non-conducting state and SSSPs 92 and 96 are energized to the conducting state by an output pulse 118 from switch logic circuit 88 through diodes 113 and 115. When the current at 106 is positive with respect to ground 108, and accept pulse is generated from comparator 98 to magnitude flip-flop 86 so that SSSPs 90 and 94 are not de-energized. The remaining ten comparisons serve to locate the synchro shaft angle within the octant established by the first three comparisons. The synchro angle shaft position is defined by either a tangent or a cotangent function. When the cosine function is larger than the sine function, the cosine function is used as a reference signal for converter 20. The signal at summing bus 106 is the sine function divided by the cosine function, which is equivalent to the tangent function of the synchro shaft angle. When the sine function is larger than the cosine function, the sine function is used as a reference signal for converter 20. The signal at summing bus 106 is the cosine function divided by the sine function, which is equivalent to the cotangent function of the synchro shaft angle.

A program pulse No. 4 is applied to a sequential flipflop network which contains a plurality of sequential flip-flops (not shown). An output pulse 121 from sequential flip-flop network is applied to SSSP 122. SSSP 122 is energized to a conducting state so that a current flows through a resistor 124. When the current at summing bus 106 is negative with respect to ground 108, a reject pulse is generated by comparator 98 so that SSSP 122 is de-energized to the non-conducting state. When the current at 106 is positive with respect to ground 108, a accept pulse is generated by comparator 98 so that SSSP 122 is not de-energized. The conversion is completed after a program pulse No. 13, for example, is applied to SSSP 126 and either a reject pulse or an accept pulse is generated by comparator 98. The final state of each sequential flip-flop in the sequential flip-flop network 120 represents one bit of the digital signal at output terminal. 22, which delineates the synchro shaft position in digital form.

FIG. 2 illustrates an eight bit multiplying AC or DC reference digital to anlog converter. Generally, the converter comprises an input terminal 128 for receiving a digital signal, a voltage source 130 for supplying a reference voltage, a reference control logic 132 for controlling the reference voltage, a sampling network 134 comprising a sequence of precision voltage components, for example, resistors, a switching network 136 comprising a plurality of SSSP switches for controlling current flow through the precision voltage components, a control register 138 for controlling the conduction state of the SSSP switches, and an amplifier network 140 for presenting the digital signal in analog form. In the illustrated'converter, the sampling network includes eight SSSP switches. It will be understood that, in alternative embodiments, the number of SSSP switches is other than eight, for example, 12.

In the device of 'FIG. 2, a digital signal is applied at 142 to input terminal 128. The digital signal from the input terminal 128 is applied to control register 138. Each output signal from control register 138 is determined by the digital bit applied thereto, i.e., a signal SSSP is connected to one of the precision resistors in sampling network 134. Thus SSSP 148 is connected to precision resistor 152. SSSP 150 is connected to precision resistor 154, etc. A predetermined voltage from the voltage source 132 is applied to ajunction 156, the union of the precision resistors in sampling network 134.

The predetermined voltage from the voltage source is generated from either a positive AC reference voltage supply 158, a negative AC reference voltage supply 160 or a DC reference voltage supply 162. Reference voltage supplies 158, 160 and 162 are connected to SSSPs 164, 166 and 168, respectively. Each of SSSP switches 164, 166 and 168 is controlled by reference control logic 132. When a positive AC reference voltage is required, a signal 170 from the reference control logic is applied to SSSP 164. Next SSSP 164 is energized to the conducting state and a positive AC refer ence voltage 172 is applied to junction 156. When a negative AC reference voltage is required, a signal 174 from the reference control logic circuit is applied to SSSP 166. Then SSSP 166 is energized to the conducting state and a negative AC reference voltage 176 is applied to junction 156. When an SSSP in the switching network is in the conducting state, a predetermined current is permitted to flow from junction 156 through the corresponding precision resistors to junction 178.

The value of each precision resistor is so weighted that the current through each contributes to a current at junction 178. The current at 178 generates a voltage across a feedback resistor 180 of amplifier 181. Hence, the voltage at output 182 is proportional to the current at junction 178. As previously stated, the current at 178 is dependent upon the conducting state of the SSSP switches in sampling network 136. Therefore, the voltage at output 182 represents the digital signal multiplied by the reference voltage at 156 in analog form.

Since certain changes may be made in the foregoing disclosure without departing from the scope of the invention herein involved, it is intended that all matter contained in the above description and shown in the accompanying drawings be construed in an illustrative and not in a limiting sense.

What is claimed is:

l. A device for switching voltage, said device comprising:

a. inputmeans;

b. impedance means for changing an input voltage at said input means to a current;

0. operational amplifier means having input and output terminals, a virtual ground presented at said operational amplifier means input terminal;

(1. output means;

e. a first solid state switch, said first solid state switch having energized and deenergized states; and

f. a second solid state switch, said second solid state switch having energized and denergized states;

g. said impedance means serially connected between said input means and said first solid state switch, said impedance means and said first solid state switch connected at a first junction, said first solid state switch connected between said first junction and a ground;

h. said second solid state switch serially connected between said first junction and said operational amplifier means input terminal, said second solid state switch and said operational amplifier means input terminal connected at a second junction;

i. said operational amplifier means output terminal connected to said output means;

j. said current switched to said ground when said first solid state switch is in said energized state and said second solid state swtich is in said deenergized state, said current switched to said virtual ground when said second solid state switch is in said energized state and said first solid state switch is in said deenergized state, whereby a constant impedance is presented at said input means.

2. The switching device as claimed in claim 1 including feedback means serially connected between said operational amplifier means input and output terminals.,

3. The switching device as claimed in claim 1 wherein said first solid state switch is a field effect transistor and said second solid state switch is a field effect transistor. 4 l fi '5 l

Claims (3)

1. A device for switching voltage, said device comprising: a. input means; b. impedance means for changing an input voltage at said input means to a current; c. operational amplifier means having input and output terminals, a virtual ground presented at said operational amplifier means input terminal; d. output means; e. a first solid state switch, said first solid state switch having energized and deenergized states; and f. a second solid state switch, said second solid state switch having energized and denergized states; g. said impedance means serially connected between said input means and said first solid state switch, said impedance means and said first solid state switch connected at a first junction, said first solid state switch connected between said first junction and a ground; h. said second solid state switch serially connected between said first junction and said operational amplifier means input terminal, said second solid state switch and said operational amplifier means input terminal connected at a second junction; i. said operational amplifier means output terminal connected to said output means; j. said current switched to said ground when said first solid state switch is in said energized state and said second solid state swtich is in said deenergized state, said current switched to said virtual ground when said second solid state switch is in said energized state and said first solid state switch is in said deenergized state, whereby a constant impedance is presented at said input means.

2. The switching device as claimed in claim 1 including feedback means serially connected between said operational amplifier means input and output terminals.

3. The switching device as claimed in claim 1 wherein said first solid state switch is a field effect transistor and said second solid state switch is a field effect transistor.

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