DE3525174C2 - - Google Patents

Description

The invention relates to a circuit arrangement, the a carrier signal in its frequency keyed and at the this carrier signal to be modulated an input of a having a control input and an integrator Modulation circuit is supplied.

For the transmission of several signals, especially of Digital signals, via a common transmission channel frequency division multiplex systems are preferred. The Modulation methods used for the transmission of digital signals frequency shift keying (FSK) is based on that depending on the logical state of the transmission Signals, between (at least) two output frequencies is keyed.

An arrangement for performing such a method is known from DE 24 43 286 A1. In this there is the transmitter from a quartz-stabilized transmitter Oscillator, which is followed by a frequency divider. This is followed by a mixer to which the output signal is also sent of the oscillator. At the exit of the mixer two bandpasses connected to two different ones Frequencies are tuned. The output signals of the Bandpasses are fed to a changeover switch that is operated by the digital signal to be transmitted is controlled. At the exit of the switch occurs depending on the state of the digital signal either one or the other frequency of the Bandpasses on.

Another is a frequency modulator in DE 31 13 800 A1 described with a phase modulator. The Carrier signal input of the phase modulator from one Carrier signal generator and the modulation signal input from fed to an integrator. To avoid that Integrator output signal has reached extremely high values an adjustable frequency divider in the carrier signal path recorded by the phase modulator. If the integrator output signal crosses a first threshold,  a switch closes, causing the charge in the integrator capacitor reduced through a resistor and the phase shift caused by the phase modulator changed becomes.

Each signal to be transmitted is in a transmitter circuit consisting of a modulator and a downstream one Filter circuit implemented. The output signals of everyone of these transmitter circuits are added and over the Transmission channel transmitted to the receiver.

Filter circuits to limit the spectrum of the Output signals of the individual transmitter circuits are in generally necessary because the spectrum of a frequency-clocked Theoretically, signals are infinitely wide, and therefore, in order to influence each other neighboring To prevent channels must be limited.

In known systems of this type, especially for transmission of digital signals, the transmission frequency is the Transmitter circuit (= channel frequency) by frequency determining Fixed components; the maximal Clock rate of the digital signal to be transmitted can be from Operator of the transmitter circuit cannot be increased.

For the manufacturer of such transmission systems revealed thereby the disadvantage that per channel frequency and Transmission speed each a different transmitter type should be present. In practice that meant with a typical number of 24 channel frequencies at 50 Band and 5 different clock rates (50, 100, 200, 600 and 1200 baud) that a total of 46 different transmitter types would have to be manufactured and stored in stock. Also for this large variety of types had disadvantages for users connected, since already when planning a system the final configuration had to be determined and was very difficult to change afterwards.  

A simplification when planning such Transmission systems resulted from the fact that so-called "frequency-neutral" transmitter circuits were constructed, where the user can change the transmission frequency of switching bridges on the finished device. As a result of the measure, the range of types was reduced to one type per transmission speed, independently from the channel frequency. The transmission speed itself is also with these transmitter circuits fixed, since the filter circuits only for designed a certain transmission speed could become. The change in transmission speed is also only with exchange with these devices the entire transmitter circuit or at least a part possible.

The object of the invention is to provide a circuit arrangement realize at which the carrier frequency of the transmitter signal is continuously and / or adjustable in stages and at which the clock rate of the signal to be transmitted is variable.

This object is achieved in a circuit arrangement of the type mentioned in the present invention in that the Modulation circuit has two outputs and that Carrier signal is modulated so that at the first output a first output signal

and to the second output a second output signal

is given, where ω _{H is} an arbitrary selectable, the modulation index defining auxiliary circuit frequency of the modulation circuit ( 1 ), U _E (t) the carrier signal to be modulated and ψ ₁, ψ ₂ are arbitrarily selectable, constant phase angles, whereby applies

and that a multiplier circuit is connected to each output of the modulation circuit, which multiplies the output signal of the modulation circuit by a harmonic oscillation of an angular frequency ω _K , the harmonic oscillation of one multiplier circuit having a constant phase shift with respect to the harmonic oscillation of the other multiplier circuit, and that Output signals (K _{AM 1} and K _{AM 2} ) of the two multiplier circuits ( 4, 5 ) are fed to the two inputs (E) of a summing circuit ( 6 ), at whose output connection (A) the frequency-gated transmitter signal is emitted.

The frequency ω _{K of} the harmonic oscillations with which the output signals of the modulation circuit are linked in the multiplier circuits indicates the carrier frequency of the frequency-clocked signal generated.

Refinements of the circuit arrangement according to the invention, especially the modulation circuit Removable subclaims.

One of these configurations consists of the fact that the second input is led out in each multiplier circuit and that a harmonic oscillation with the angular frequency ω _K is present at each of these inputs. In this way, a variation of the carrier frequency can be achieved in a particularly simple manner.

The harmonic vibration is generated externally.  

Another advantage of the invention is that each multiplier circuit comprises an oscillation generator which generates a harmonic oscillation with the angular frequency ω _K.

The modulation index of the generated frequency-clocked signal, or the frequency swing for digital modulation signals, is determined by the auxiliary circuit frequency ω _{H of} the modulation circuit.

The auxiliary circuit frequency ω _{H of} the modulator can be controlled via the control input of the modulation circuit, as a result of which the modulation index can be set, and thus any transmission speeds in the circuit arrangement according to the invention are possible within wide limits.

The invention is described below with reference to FIG Described drawings. It shows

Fig. 1 is a block diagram showing the circuit arrangement of the invention;

Fig. 2ac 2aa-line diagrams of the output signals of the circuit of Fig. 1;

Fig. 3 shows a possible embodiment of a modulation circuit according to the invention in analog technology;

Fig. 4 line diagrams of the input and output signals of the circuit of Fig. 3;

Fig. 5a, b digital realizations of the inventive circuit arrangement and

Fig. 6 shows the time of two internal signals and the output signals of the circuit of FIG. 5a.

Fig. 1 shows the block diagram of the circuit arrangement according to the invention, which keyed the frequency of a carrier signal.

The signal to be transmitted U _E is fed to an input E of a modulation circuit 1, two output signals U _{A 1} and _{A 2} U generated. The frequency deviation of the frequency-clocked transmitter signal generated in the circuit can be set via a further input S 1 of the modulation circuit. The control input S ₁ can be omitted if the frequency swing of the transmitter signal need not be changeable.

Each output A ₁ or A ₂ of the modulation circuit 1 is in each case via a filter circuit 2 or 3 to the input of a multiplier circuit 4 or 5 . The low-pass filter circuits 2, 3 of the same type serve to limit the spectrum of the frequency-clocked signal and are generally only necessary to comply with regulations of the telecommunications authorities; If such regulations regarding the maximum spectral width of the transmission signal do not apply, or if the input signal U _E fulfills certain criteria, the filter circuits 2, 3 can be omitted.

In the multiplication circuit 4 or 5 , the product of the respective input signal of the multiplication circuit and one harmonic oscillations which are out of phase with the other multiplication circuit, but have the same frequency, are formed. The respective product signal is present at the output A _{M 1} or A _{M 2} . The harmonic oscillation can either be generated in the multiplier circuit 4 or 5 itself, the frequency of the oscillation optionally being set via a control input S _{M 1} or S _{M 2} , or it can be set externally in a common, again controllable generator generated and be guided to the multiplier 4 or 5 via a downstream phase splitter circuit via the control input S _{M 1} or S _{M 2} .

The two outputs A _{M 1} , A _{M 2 of} the multiplier circuits 4, 5 are fed to the inputs of a summing circuit 6 and there are additively linked to the output signal of the circuit arrangement U _A , which is present at the output A of the summing circuit 6 .

In the following, the overall function of the circuit arrangement will first be described using the block diagram in FIG. 1.

The input signal U _E should generally be described by the time function U _E (t). For the transmission of digital signals, the input function U _E , depending on the logic state, can be assumed to be U _E = 1 or U _E = -1.

In the modulation circuit 1 , two output signals U _{A 1} , U _{A 2 are} generated, which correspond to the equations

Here, ω _{H is} an arbitrarily selectable, constant auxiliary circuit frequency, which indicates the modulation index η of the frequency-clocked signal, or in the case of digital input signals U _E , the frequency deviation of the generated FSK signal.

In principle, the two phase angles ψ ₁, ψ ₂ can be freely selected as long as they do not differ from one another by integer multiples of π . For simplification, the two phase angles with ψ ₁ = 0 and ψ ₂ = π / 2 are assumed for the following description.

The output signals of the modulation circuit 1 are thus calculated

If the influence of the low-pass filter circuit 2, 3 is neglected for the following consideration, these signals are present at the inputs of the multiplier circuit 3, 4 . The signals U _{AM 1} and U _{AM 2 are} emitted at their outputs.

The output signal of summer 6 thus results in:

In the above equation, U _E can have any dependence on t . The constant logic states U _E = +1 and U _E = -1 that preferably occur in the circuit according to the invention are used below.

With U _E = +1 for t greater than t U U _A (t) = sin · [ ( ω _k + ω _H ) · t + ψ ₀].
-

With U _E = -1 for t greater than t ₀ U _A (t) = sin · [ ( ω _k - ω _H ) · t + c ₀].
-

It can be seen from the above equations that the output voltage U _A is a frequency-clocked signal. The center frequency of the signal (= channel frequency) is determined by the frequency of the harmonic oscillation used in the multiplier 4 or 5 with the angular frequency ω _{K which} may be variable via the control inputs S _{M 1} , S _{M 2} . The symmetrical frequency deviation is determined by the angular frequency ω _H used in the modulator and possibly changeable via the control input S ₁. In the modulation circuit 1 1 of the frequency deviation +/- l _H is generated around the center frequency ω _K = 0 by the input voltage U _E = +/-. With this switchover between + ω _H and - l _{H there} are discontinuities in the signal curve of the output signals U _{A 1} and U _{A 2 of} the modulation circuit 1 , but no jumps.

In order to make the processes in the modulation circuit 1 and the entire circuit easier to understand, the line diagrams of the output signals U _{A 1} and U _{A 2 of} the modulation circuit 1 for the switching times π , 7 π / 4 and 5 π are shown in FIGS . 2aa to 2ac / 4 shown.

Depending on the phase position after these switching times from U _E = +1 to U _E = -1, the following output voltage results in accordance with the equation given above:

Example 1 ( Fig. 2aa): U _E from +1 to -1 according to π

for U _E = +1:
U _A (t) = sin ω _K tcos ω _H t + cos ω _K tsin ω _H t = sin ( ω _K + - ω _H ) t

for U _E = -1:
U _A (t) = sin ω _K tcos ω _H t - cos ω _K tsin ω _H t = sin ( ω _K - - ω _H ) t

Example 2 ( Fig. 2ab): U _E from +1 to -1 after 7 π / 4

for U _E = +1:
U _A (t) = sin l _K t · cos ω _H t + cos ω _K t · sin ω _H t = sin ( ω _K + - ω _H ) · t

for U _E = -1:
U _A (t) = -cos ω _K t · cos ω _H t - sin ω t ⋅ sin ω _{K H} · t = cos (ω _K - - ω ₀) · t

Example 3 (Figure 2a-c.): U _E from +1 to -1 after 5 π / 4

for U _E = -1:
U _A (t) = sin l _K t · cos ω _H t + cos ω _K t · sin ω _H t = sin · ( ω _K - + ω _H ) · t

for U _E = -1:
U _A (t) = sin ω _K t · sin ω _H t - cos ω t ⋅ cos _K l _H t = cos (ω _K - - ω _H) · t.

It should be mentioned here that the circuit according to the invention is not limited to modulation circuits whose output signals U _{A 1} and U _{A 2 have a} 90 ° phase shift with respect to one another; phase shifts of the two signals that deviate from 90 ° but are constant are also possible. Likewise, the phase difference of the harmonic oscillations with which the signals U _{A 1} and U _{A 2} in the multiplier circuits 4 and 5 are linked is not restricted to the value 90 °. However, this value leads to a particularly descriptive mathematical description of the function of the circuit arrangement according to the invention.

Fig. 3 shows the detailed block diagram of a possible implementation of the modulation circuit in analog technology.

The input signal U _E is fed to the integration input of an integrator 7 and to a sign input of a comparator 8 . At two further inputs of the comparator there are two fixed values U _{K +} and U _{K -} which indicate the limits of the integration range of the integrator. The output of the integrator is connected to the comparison input of the comparator, the output of the comparator is connected to the reset input of the integrator. The inputs of two function generators 9, 10 , whose outputs deliver the output signals U _{A 1} and U _{A 2} , are also connected to the output of the integrator.

Figs. 4a shows a typical time course Sichen a digital input signal U _E; FIG. 4b shows the output signal U _I of the integrator 7 and Fig. 4c and Fig. 4d, the respective outputs of the function generators 9, 10 is.

.. Below with reference to Figures 3 and 4, the basic function of the modulation circuit will be described:

The input signal UE (input data) is fed to the integrator 7 and as a sign recognition signal to the comparator 8 . The direction of integration is determined by the sign of the input voltage. The limits for the output voltage of the integrator 7 are predetermined by the voltages U _{K +} and U _{K - which} are permanently applied to the comparator 8 . With a positive input voltage U _E is integrated from U _{K +} to U _{K -} , with a negative input voltage from U _{K -} to U _{K +} ( Fig. 4a, b).

The input voltage U _E , the time constant of the integrator 7 and the limits of the integration range U _{K +} and U _{K -} are adjusted so that the desired period 2 π / ω _H of the sawtooth voltage U _I output by the integrator is achieved.

The periodic sawtooth voltage U _I is preferably fed to two function generators which convert the periodic sawtooth voltage U _I into periodic output voltage U _{A 1} , U _{A 2} with the same period as U _I and U _{A 2 is out of} phase. Preferably, as shown in Fig. 4c and Fig. 4d, the voltage U _I in a function generator 9 (10) in a sinusoidal voltage U _{A 1} and in another function generator 10 (9) into a cosine voltage U _{A 2} converted.

The Fig. 5a shows a possible implementation of the modulation circuit in digital technology.

The (digital) input signal U _E is applied to the count direction input of an up-down counter 11 ; a clock signal S 1 is present at the clock input of the counter, which is either generated in an internal clock generator 12 or generated externally and supplied via the control input S 1 .

The parallel output lines of the counter 11 form the data bus B 1, which is connected to the address inputs of a first analog multiplexer 13 and is led via an adder circuit 15 to the address inputs of a second analog multiplexer 14 . In the adder circuit 15 , a fixed value, which is generated by the coding switch 18 and is present at the second inputs of the adder circuit 15, is added to the respective digital word on the bus B 1 .

Each of the analog inputs of one multiplexer is connected in pairs to the corresponding input of the other multiplexer and is led to a tap of a resistance voltage divider chain 17 , which is fed by a voltage source 16 .

In the following, 5a and 6, the function of the modulation circuit is described in a digital embodiment with reference to FIG...

The counter 11 counts up or down depending on the polarity of the input voltage U _E and thus fulfills the function of an integrator. The integration time constant can be set with the clock frequency of the clock generator 12 .

By overflowing the counter after the period 2 π / ω _H , a quasi sawtooth function is achieved in a simple manner in the data bus B 1 , because after the binary number 1111 the counter starts counting again with the binary number 0000. Functionally, the signal sequence on data bus B 1 corresponds to signal U _I in FIG. 4b.

The data bus signal B 1 is supplied on the one hand to a multiplexer 13 and on the other hand to an adder 15 . The multiplexer 13 converts this signal in a known manner into a periodic output voltage U _{A 1} , which is preferably designed as a sinusoidal voltage with the period 2π / ω _H.

In order to achieve a voltage U _{A 2} phase-shifted to U _{A 1} at the output of the second multiplexer 14, a numerical value is entered at the input of the multiplexer 14 via the data bus B 2 , which differs from the numerical value of the data bus B 1 by the value that causes the desired phase shift. In a simple manner it is achieved that those desired number is added to the value in B 1 with the adder 15, which is set by the coding 18th

In FIG. 6, it is shown how in accordance with the data bus signals B 1 and B is formed step-shaped, the quasi-sinusoidal voltage to U _{A 1} and the quasi-cosine of U _{A 2} 2. It can also be seen that the phase shift between U _{A 1} and U _A 2 corresponds to a numerical value difference of binary 0100 between B 1 and B 2 .

6 is also shown in Fig. Similar to Fig. 4c and 4d shows how the output voltages U _A U _{A 1} and ₂ run at the time when 2 π / ω _H, the input signal U _E of +1 changes to -1.

Up to the point in time 2π / 1 _H, the counter 11 counts in the upward direction and a quasi-sine voltage arises at the output U _{A 1} . From the time π 2 / l _H counts of the counter 11 in a downward direction and at the output U _{A 1} produces a quasi-minus-sine wave voltage.

The circuit shown in FIG. 5a is only an example. The same principle can also be solved differently in digital technology. For example, according to FIG. 5b, instead of the two multiplexers 13 and 14, digital-to-analog converters 20, 21 can be used, which convert the data bus signal B 1 into the desired output signal U _{A 1} or U via upstream conversion tables 18, 19 stored in a memory Form _{A 2} .

It can be used the basic circuit of FIG. 1, the modulation circuit of Fig. 3 and the digital modulation circuit according to Fig. 5a and b used as a basis for the programming of a microprocessor, and thus realization of the circuit arrangement according to the invention be accomplished in microprocessor technology.

Claims (8)

1. A circuit arrangement which keys a frequency of a carrier signal and in which this carrier signal to be modulated is fed to an input of a modulation circuit having a control input and an integrator, characterized in that the modulation circuit ( 1 ) has two outputs (A ₁, A ₂ ) and the carrier signal (U _E ) is modulated so that a first output signal at the first output (A ₁ ) and at the second output (A ₂ ) a second output signal is given, where ω _{H is} an arbitrary selectable, the modulation index defining auxiliary circuit frequency of the modulation circuit ( 1 ), U _E (t) the carrier signal to be modulated and ψ ₁, ψ ₂ are arbitrarily selectable, constant phase angles, whereby applies and that a multiplier circuit ( 4 or 5 ) is connected to each output of the modulation circuit ( 1 ), which multiplies the output signal (U _{A 1} or U _{A 2} ) of the modulation circuit ( 1 ) by a harmonic oscillation of an angular frequency ω _K , wherein the harmonic oscillation of one multiplier circuit ( 4 ) has a constant phase shift with respect to the harmonic oscillation of the other multiplier circuit ( 5 ), and that the output signals (U _{AM 1} and U _{AM 2} ) of the two multiplier circuits ( 4, 5 ) are at the two inputs (E) are fed to a summing circuit ( 6 ), at whose output connection (A) the frequency-gated transmitter signal (U _A ) is emitted. 2. Circuit arrangement according to claim 1, characterized in that the integrator ( 7 ) in the modulation circuit ( 1 ), a comparator ( 8 ) is connected in parallel, with the input of a first and the at the output (U _I ) of the integrator ( 7 ) Input of a second function generator ( 9 or 10 ) is connected and at the output of one function generator ( 9 ) the one output signal (U _{A 1} ) of the modulation circuit ( 1 ) and at the output of the other function generator ( 10 ) the other output signal (U _{A 2} ) of the modulation circuit ( 1 ) ( Fig. 3). 3. Circuit arrangement according to claim 1, characterized in that the modulation circuit ( 1 ) has a clocked up-down counter ( 11 ), at whose direction changeover input the carrier signal to be modulated (U _E ) is applied, with the output data bus (B ₁ ) of the up-down counter ( 11 ) a first analog multiplexer circuit ( 13 ), and via an adder circuit ( 15 ) a second analog multiplexer circuit ( 14 ) is connected, the analog inputs of the multiplexer circuits being at different voltages which are preferably realized by taps on a voltage divider circuit (14), and wherein the output signals (U _{a 1} and U _{a 2)} of the modulation circuit (1) multiplexer circuit analog (13 and 14) are tapped to the analog outputs of the ( Fig. 5a). 4. Circuit arrangement according to claim 1 or 3, characterized in that the modulation circuit ( 1 ) has a clocked up-down counter ( 11 ), and that on the output data bus (B 1 ) of the up-down counter two digital-analog Converter circuits ( 20 or 21 ) are each connected via an upstream conversion circuit ( 18 or 19 ), and the output signals (U _{A 1} or U _{A 2} ) of the modulation circuit ( 1st ) are connected to the analog outputs of the digital-analog converter circuits ( 20, 21 ) ) can be tapped ( Fig. 5b). 5. Circuit arrangement according to claim 1 to 4, characterized in that the auxiliary circuit frequency ( ω _H ) of the modulator can be controlled via the control input (S 1 ) of the modulation circuit ( 1 ). 6. Circuit arrangement according to one of claims 1 to 5, characterized in that with each multiplier circuit ( 4 or 5 ) the respective second input (S _{M 1} or S _{M 2} ) is brought out, and that a harmonic oscillation at each of these inputs with the angular frequency ( ω _K ). 7. Circuit arrangement according to one of claims 1 to 5, characterized in that each multiplier circuit ( 4 or 5 ) comprises a vibration generator which generates a harmonic vibration with the angular frequency ( ω _K ). 8. Circuit arrangement according to one of claims 1 to 7, characterized in that between each output (U _{A 1} , U _{A 2} ) of the modulation circuit ( 1 ) and the associated multiplier circuit ( 4 or 5 ), a low-pass filter circuit ( 2 or 3 ) is arranged.