DE3722125A1 - Method for pulse duration modulation and circuit arrangement for carrying out the method - Google Patents

Abstract

In this method and arrangement, for improving the bandwidth/transmission time ratio with respect to a transmission, an N-position digital word is divided into ng part words in each case with the number of positions N/(ng) and the part words, before they are transmitted on a signal path, are converted into a number of pulses corresponding to the number ng of the part words with durations proportional to the contents of the part words and the position values coresponding to the position values of the part words. The invention is used especially in the data transmission of measurement data obtained in accordance with the time divider method. <IMAGE>

Description

In measurement and process technology, communications engineering and The problem arises when using electronic computers, analog ones Sizes at a sending location in the form of analog or digital signals map and with the greatest possible interference immunity, reliability and image fidelity with the lowest possible Ge total effort over a greater or lesser distance to one Transfer point of receipt.

Very often there is the additional desire to have this data transmission over a common ring or bus line between a larger number of spatially distributed transmit and emp traps according to one of the established multiplexing methods to be able to make.

The following data transmission methods are common:

1. Digital data transfers

The analog quantity is quantized on the transmission side in a suitable code and represented as a "date" in the form of an N -digit binary pattern. There are essentially three methods available for the transmission of such digitally encrypted data.

• 1.1 Parallel data transmission is understood when each of the N binary positions is transmitted on its own data channel. This process is very fast, but requires a lot of effort.
• 1.2 With the so-called serial data transmission, only one data channel is used, over which the N binary digits are transmitted one after the other. The effort required for cables is naturally small, but there are synchronization problems between the sender and receiver. The transfer is relatively slow.
• 1.3 In the case of bit-parallel, byte-serial data transmission, the N binary digits of a date are grouped into n _g group words Binary digits (bits) divided. N and n _g are chosen so that the number of digits n _{w of} the word length is an integer. A word length of n _w = 8 has been introduced. The eight bits are called 1 byte. The last-mentioned type of data transmission is to be regarded as a compromise between the methods specified under 1.1 and 1.2. The individual words (bytes) are transmitted sequentially (serially) over parallel (bit parallel) data channels.

2. Analog data transfers

The analog size is different on the transmission side specific characteristics of a mostly electrical signal carrier modulated and this analog signal via channel paths transferred to the recipient. Only then does the recipient find it Digitization necessary for digital data processing of the received signal instead. In addition to the amplitude, Phase and pulse position modulation have the following two Signal modulation gained importance in this context.

• 2.1 Frequency analog signal transmission (FM):
  In this method, the frequency of an alternating quantity (alternating voltage) of the analog quantity to be transmitted is made proportional. This is a very interference-free type of transmission because damping and delay distortion do not represent an error. On the receiver side, there is a simple digitization option through counting in conjunction with a stable time reference. Either the period or the number of zero crossings during a reference time can be counted.
• 2.2 Pulse length analog signal transmission (PLM):
  The invention is based on this modulation method. In this method, an analog variable is mapped in a rectangular pulse of the duration τ , where τ is proportional to the analog variable a . It is Here, α is the quotient in the above expression and T _{S, E is} the reference time on the transmitting side and on the receiving side.
  In some cases, for the sake of simplicity, the reference time T _{S, E} on the transmitter side and receiver side is set equal and kept constant. Then simple number circuits in connection with a quartz oscillator are sufficient to digitize the signal in the receiver by counting the quartz pulses for the duration τ _E into a counter.
  In other cases, this method is varied in that the transmitter also specifies the reference time T _S and the analog information in the ratio of the pulse duration to this reference time is shown: This process is also called time divider or "time division" process in Anglo-Saxon literature. The digitization of messages transmitted in this way is somewhat more complex than with the method mentioned under 2.1; however, if a computer is available, it is completely unproblematic and therefore also fully computer-compatible.
  Despite their simple operation, the pulse-length analog signal transmission has not yet found widespread use, in particular in connection with electronic computers. This is mainly due to the fact that relatively short transmission distances on simple connecting lines give rise to runtime distortions. This results in deteriorations in the slope of the signal pulses to be transmitted. The signal pulses can receive the edge part required for the analog-digital conversion again at the receiving end by means of a pulse shaper stage (Schmitt trigger), but the accuracy of this conversion remains more limited the more the edges of the pulses are ground.
  If a given accuracy of the implementation - expressed by a corresponding number of digits N of the data - is required, this can be done either by reducing the transmission speed, ie increasing T _S at a constant ratio or by using broadband transmission channels, for example coaxial cables, and thus a greater amount of transmission is required if larger distances have to be bridged.

The invention was based on the object of a method for Length modulation of pulses and a circuit arrangement for The exercise of this procedure, with which the bandwidth Transmission time ratio compared to the known pulse lengths modulation can be improved.

This task is solved procedurally in that an N -digit digital word (signal) in n _g partial words each with the number of digits

is broken down and that the subwords are converted in a signal path into a number of pulses corresponding to the number n _{g of} the subwords with lengths of the contents of the subwords and lengths corresponding to the position values of the subwords. Length-modulated pulses are therefore transmitted, each of which only a part

of the entire date. The partial data are also subject to smoothing on the transmission path between sender and receiver, but are due to the on division into groups of different importance less overall Bits needed to transmit the entire date and therefore Time saved.

A Ready can be used for transmission on parallel channels position of the pulse-length-modulated pulses on position value signals fictitious parallel outputs of a transmitter.

For serial transmission of the entire date on one The second channel provides the pulse length modulation th impulses for a serial corresponding to their importance Output on a single outlet. The Be is then expedient beginning or end of a single date pulse follow the sequence by reversing the polarity of the first or last pulse marked.

The pulse lengths can be set on the transmitter side without great effort represented by the duration of trains of higher-frequency impulses. This signal form has the advantage that simple counters on The place of destination receives the data directly into the associated digital words can be implemented.

In a circuit arrangement for executing the method Bit outputs of a multi-level buffer for a digita les signal with corresponding bit inputs of a digital ver the same number of stages connected, its comparison bit inputs are at bit outputs of a clock counter. Farther is a transmission pulse output of the clock counter on each first control inputs of two flip-flops connected, whose second control inputs each with one of two the same corresponding bits in two groups with higher or low level of summarized levels of digital Comparator marking signals connected outputs connected are. Then par at the signal outputs of the two flip-flops allel two the content of the twi, divided into two sub-words length-modulated pulses will.

A circuit arrangement for the delivery of serially transferable Pulse is compared to the arrangement described above to the extent that the signal outputs of the two flip- Flops additionally at the first inputs of two AND gates lie, of which second inputs each with a different one from two outputs of a third flip-flop are connected, at the Switching input of the carry pulse output of the clock counter connected. The signal output of one AND Gate via a polarity reversal stage to the signal output of the other AND gate connected in parallel. At the common exit of the AND gates are proportional to the content of the buffer length-modulated pulses can be removed serially.

To the circuit arrangement for delivering in parallel at the output make pending impulses suitable for the display of these impulses due to the length of pulse trains of higher frequency Pulse sequences, it is sufficient to switch the signal outputs of the two flip Flops with first signal inputs of two additional ones AND gate to connect, the second signal inputs together are at a clock pulse output of a clock generator. At Outputs of the two additional AND gates can then through the Duration of pulse trains shown length-modulated pulses in parallel be removed.

A serial output by the duration of pulse trains pulse length modulated pulses is achieved that the first two AND gates each have third inputs have that with the clock pulse output of a clock generator are connected. At the common exit of the first two AND gates can then take length-modulated pulses in series become, by the duration of pulse trains of a higher fre quent clock pulse sequence are formed.

A shortening of the conversion time of the date in pulse length mod gated impulses is in the circuit arrangements presented thereby achieved that the clock-side bit inputs of the lower levels from both groups of the combined Levels of the digital comparator with corresponding bit outputs gears a first low-order level of the clock counter and the bit inputs of the higher levels from both groups corresponding bit outputs of a second higher level of the clock counter are connected.

In the following, the invention is explained in more detail with reference to 12 figures explained.

Figs. 1 and 2 refer to foundations of the modulation pulse lengths, which present the invention.

Fig. 3 is a diagram showing the degeneration of a square wave signal on a transmission channel.

In Fig. 4 an embodiment of a circuit arrangement according to the invention is shown.

Fig. 5 is a diagram illustrating the implementation of digital storage values in pulse-width modulated pulses.

In Figs. 6 to 9 of the time course of pulse lengths modulated signals to different outputs of the circuit of Fig. 4 is illustrated.

The diagrams in FIGS. 10 to 12 explain which requirements have to be made for the regeneration of a transmitted square-wave signal.

In Fig. 1, a pulse-length-modulated signal is shown, as it underlies the prior art of 2.2. The abscissa represents the time axis t , while a pulse-length-modulated transmission signal u is plotted on the ordinate. Permanently modulated positive pulses with a pulse duration τ can be seen within reference times T _{S, E.} The relationships specified under 2.2 in the introduction apply to this signal.

FIG. 2 shows the receiving side for a pulse-length-modulated signal in the manner of the diagram shown in FIG. 1. A signal ü arrives at a branch point P via a transmission line L. From there, the signal reaches the control input of a flip-flop FF via a differentiating stage DIF . Furthermore, the signal ü is fed via the branch point P to one of the inputs of one of two AND gates UN . The output of the flip-flop FF is connected to one input of the other of the AND gate UN . Two diodes of a filter circuit SI ensure that only the leading edge of the square wave above the flip-flop FF modulates. The output of a quartz oscillator Q for a clock pulse sequence is connected to second inputs of the AND gates UN . The outputs of the AND gates UN are each connected to inputs of counter stages Z _τ or Z _TS . The outputs of the counter stages are at separate inputs of a divider DIV , at the output of which a number corresponding to the analog value α can be obtained.

As can be readily seen from the figure, be directly attached to the transmission signal connected AND gate ü one of the pulse duration τ corresponding number n _τ of clock pulses of the crystal oscillator Q supplied to the counting stage Z _τ. In contrast, the AND gate connected to the flip-flop FF allows a number n _T of pulses of the quartz oscillator Q corresponding to the duration of the reference time to be passed to the counter Z _TS . These numbers are processed in the divider DIV to the analog value α .

In the diagram of FIG. 3, a square wave signal U _{S is} shown as it is given by a transmitter on a line. The signal ü _{E, which is} shown at the same time after transmission, shows the known degeneration phenomena in the diagram. It is delayed in time, its amplitude is damped compared to the original signal and its rising and falling edges have clearly finite rise and fall times. That is, they are flattened against the steep edges of the original signal. This phenomenon will be discussed again later with FIGS. 10 to 12.

In Fig. 4, a circuit arrangement for practicing the United method according to the invention is shown. There, a four-stage buffer A is entered via a parallel data entry PAR or via a serial data entry SER, a digital data to be transmitted later. If necessary, these data inputs of the buffer store A are connected to corresponding data outputs of an analog-digital converter A / D. Bit outputs of the four-stage buffer A are connected to corresponding bit inputs of a digital comparator V of the same number of stages. Comparison bit inputs of the comparator V are at bit outputs of a clock counter ZT , in such a way that clock-side bit inputs of the lower-order stages VE, VH of stages of the digital comparator V combined into two groups Vu and Vo , with corresponding bit outputs of a first lower-order stage ZTE of the clock counter ZT and the bit inputs of the higher order stages VZ, VT of the two groups Vu and Vo are connected to corresponding bit outputs of a second higher order stage ZTZ of the two-stage clock counter ZT . A transmission pulse output ÜT of the clock counter ZT is connected to first control inputs of two flip-flops FF 1 and FF 2 , respectively. Second control inputs of the flip-flops FF 1 and FF 2 are each with one of two bits corresponding to the equality of the signals U and O leading to the stages of the digital comparator V which combine the steps in two groups Vu or Vo with higher or lower position values connected. At signal outputs S 1 and S 2 of the two flip-flops FF 1 and FF 2 , two length- modulated pulses proportional to the content of the buffer store A divided into two bit words can be seen in parallel .

The signal outputs S 1 and S 2 of the two flip-flops FF 1 and FF 2 are additionally connected to first inputs of two AND gates U 1 and U 2 . Second inputs of these AND gates are each connected to another of two outputs of a third flip-flop FF 3 , at the switch input of which the transmission pulse output OT of the clock counter ZT is located. The signal output of one AND gate U 2 is connected in parallel to the signal output of the other AND gate U 1 via a polarity reversal stage IN . In addition, the signal outputs S 1 , S 2 of the two flip-flops FF 1 , FF 2 are each connected to first signal outputs of two AND gates U 3 and U 4 . Second signal inputs of these AND gates U 3 and U 4 are together at a clock pulse output of a clock generator GT .

The mode of operation of the circuit arrangement according to FIG. 4 will be explained below. For example, the circuit arrangement should be used to prepare a digital value a = 4 456 encrypted according to the BCD code for transmission. This Digi talwert can, as already mentioned, either in parallel on the four circuits AE then formed as a BCD buffer. . . AT of buffer A can be entered. Serial input is also possible if the storage decades AE . . . AT form a BCD shift register. The 16-digit digital value is divided into two group words (n _g = 2) of 8 bits each, of which the first word is the one and ten decades of AE and AZ and the second group word is the hundreds and thousands of decade AH and AT includes.

The content of both words is constantly compared via the comparator groups Vu and Vo with the content n _{T of} the two-decade BCD clock counter ZT , which is continuously counted up by the pulses of the clock generator GT with the clock frequency from 00 to 99. When its final value n _{T max} = 100 is reached, the counter ZT sets the two flip-flop stages FF 1 and FF 2 on the output side with its transmission pulse ü _T. This signal is pending until the associated comparator groups Vu and Vo report the equality of the words stored in the buffer A with the counter content n _T and reset the two flip-flops FF 1 and FF 2 . This process is shown diagrammatically in FIG. 5. It can be seen that the flip-flop FF 2 is reset after 44 period T _{t of} the clock frequency and the flip-flop FF 1 after 56 period has elapsed since delivery of a transmission pulse ü _{T of} the clock counter ZT .

This means that a pair of pulse-length-modulated signal pulses is constantly available at signal outputs Ü _Su and Ü _So , whose switch-on times τ _u and τ _o each equal the amount of the two partial words of the digital data. This signal can be transmitted separately in parallel over two transmission channels.

In the two diagrams of FIG. 6, these signals are shown in their chronological course.

Ge with little additional expenditure of the two AND gates U 3 and U 4, to the second inputs of each of the clock pulses are switched, it is alternatively possible, of the duration of pulses u _Su and u _So clocked pulse trains u _Fu and generate ü _fo.

These signals are shown in their chronological course in the two diagrams of FIG. 7.

The waveform shown has the advantage of being able to use one fold counter at the receiving location directly into the associated digital words can be implemented.

Data transmission via only one data channel is possible if the pulse-length-modulated pulses associated with the individual words are sent out serially, that is to say one after the other in time. For this purpose, the signals ü _Su and ü _{So can be given} via the AND gates U 1 and U 2 of the circuit arrangement according to FIG. 4 to a common output S 3 . With the aid of the flip-flop FF 3, which acts as a step-down stage, the two partial words are then alternately transmitted with each transmission pulse _{T of} the clock counter ZT .

The polarity reversal stage IN ensures that a synchronization and thus differentiation of the individual partial words is possible or available via the change in polarity of the transmission signal at the receiving location.

The signal ü _Sp present at the output S 3 is shown in diagram form in FIG. 8.

With the help of third inputs of the two AND gates U 1 and U 2 , which are connected together to the output of the clock generator GT , it is then also possible for the pulse durations τ _u and τ _o each of these pulse durations corresponding numbers of clock pulses to send, the polarity control can be used for word recognition at a receiving location.

The transmission _signal u _Sf generated in this way at the output S 3 can be seen from the diagram in FIG. 9.

In Fig. 10 is again a rectangular signal u _S which represented a pulse length in the modulated pulse at the transmission side, and therefore shows undistorted in its course.

Fig. 11 shows the signal u _E after its transmission via a line with a correspondingly flattened on both sides flanks.

FIG. 12 shows a signal u _reg regenerated at the receiving end.

The task to be solved at the receiving location is to generate a signal with steep flanks from the signal degenerated by the transmission with sloping flanks with the aid of a hysterical pulse shaping stage in order to be able to determine the exact temporal position of this flank; however, the distance Zvi exploiting that flanks the data to be transmitted. A Un security t _e this orientation is proportional to the formerstufe from Störsicherheitsgründen to be selected hysteresis Hy a pulse and the tangent β of an angle formed by the oblique side of the perpendicular. These variables are shown in FIG. 11 and in FIG. 12. The uncertainty t _e must be less than a time period T _t that is required for the transmission of the least significant bit of a pulse length modulated signal pulse. For a given bandwidth of the transmission channels, however, the transmission duration T _{u of} a signal pulse is determined by the number n _a of quantization steps in which a signal pulse must be resolved. The following applies to T _ü :

T _ü = t _e · n _a

Thus, in the hitherto conventional pulse-width modulated signal transmission in a word, that is n _g = 1, by one of the analog quantity per a proportionally long pulse signal, the above mentioned transmission time is needed.

When grouping n _g words in connection with the place value principle, this transmission time is reduced for serial transmission over a data channel to:

This reduction in transmission times is also a one-off sentence "New principles for analog-digital conversion and their optimal interpretation "by Karl Euler in the magazine" Fre quenz ", Volume 17, Year 1963, No. 10, especially the pages 367, right column, and 368, left column.

The ratio of the two transmission times is then:

With parallel transmission over n _g channels, the transmission duration is reduced to the value

with a corresponding favorable ratio between the over duration of a single impulse that transmits the date or of several group impulses:

In the assumed example, n _a = 10⁴ and n _g = 2. The ratio of the transmission times is then a fiftieth for serial transmission and a hundredth for parallel transmission. This gain can be used in the usual way not only to increase the transmission speed, but also optionally to improve interference immunity or to reduce the bandwidth of the transmission channel.

Finally, it should be mentioned that the design Possibilities of digital pulse length modulated signal over are particularly economical and advantageous if when digitizing the analog quantity on circuit arrangements can be used, as in EP-PS 01 41 080 are described.

Claims (7)

1. A method for the length modulation of pulses with respect to a transmission improved bandwidth transmission time ratio, characterized in that an N -digit digital word (signal) in n _g partial words each with the number of digits is broken down and that the subwords are converted into a number of pulses corresponding to the number n _{g of} the subwords with lengths of the contents of the subwords and lengths corresponding to the place values of the subwords before their transmission on a signal path. 2. The method according to claim 1, characterized in that that a provision of the pulse length modulated Pulses at parallel outputs that are significant he follows. 3. The method according to claim 1, characterized in that a provision of the pulse length mod impulses for a position that corresponds to their status serial output takes place on a single output and that the Start or end of a single date pulse follow the sequence by reversing the polarity of the first or last pulse is marked. 4. The method according to any one of claims 1 to 3, characterized characterized in that the pulse lengths by the Duration of trains of higher-frequency pulse trains are shown. 5. Circuit arrangement for carrying out the method according to claims 1 and 2, characterized in that bit outputs of a multi-stage buffer (A) for a digital signal are connected to corresponding bit inputs of a digital comparator (V) of the same number of stages, the comparison bit inputs to the bit outputs of a clock counter (ZT) lie that a transmission pulse output (ÜT) of the clock counter (ZT) is connected to first control inputs of two flip-flops (FF 1 , FF 2 ), the second control inputs of which each have one of two bits corresponding to the equality in two groups ( Vu or Vo) are connected to higher or lower positions of combined stages of the digital comparator (V) marking signals carrying outputs (U, O) , and that signal outputs (S 1 , S 2 ) of the two flip-flops ( FF 1 , FF 2 ) two parallel length-modulated pulses are present in parallel with the content of the buffer (A) divided into two partial words en. 6. Circuit arrangement according to claim 5 for carrying out the method according to claim 3, supplemented in that the signal outputs (S 1 , S 2 ) of the two flip-flops (FF 1 , FF 2 ) additionally each at first inputs of two AND gates (U 1 , U 2 ) lie, of which second inputs are each connected to another one of two outputs of a third flip-flop (FF 3 ), to the changeover input of which the carry pulse output (ÜT) of the clock counter (ZT) is connected, and that the signal output of one AND gate (U 2 ) is connected in parallel with the signal output of the other AND gate (U 1 ) via a polarity reversal stage (IN) and the AND gate (U 1 , U 2 ) is connected to the common output (S 3 ) length-modulated pulses proportional to the content of the buffer (A) can be removed serially. 7. Circuit arrangement according to claim 5 for carrying out the method according to claim 4, supplemented in that the signal outputs (S 1 , S 2 ) of the two flip-flops (FF 1 , FF 2 ) each with first signal inputs of two additional AND gates (U 3 , U 4 ) are connected, the second signal inputs are together at a clock pulse output of a clock generator (GT) , and that at the outputs of the AND gates (U 3 , U 4 ) by the duration of pulse trains from a clock pulse train mapped length-modulated Pulses can be removed in parallel. 8. Circuit arrangement according to claim 6 for carrying out the method according to claim 4, supplemented in that the two AND gates (U 1 , U 2 ) each have third inputs which are connected to the clock pulse output of a clock generator (GT) , and that at the common output (S 3 ) of the AND gates (U 1 , U 2 ), the length-modulated pulses depicted by the duration of pulse trains from a clock pulse sequence can be taken serially. 9. Circuit arrangement according to one of claims 5 to 8, characterized in that the clock counter-side bit inputs of the low-order stages (VE, VH) of both groups (Vu, Vo) of the combined stages of the digital comparator (V) with corresponding bit outputs one first low-order stage (ZTE) of the clock counter (ZT) and the bit inputs of the higher-order stages (VZ, VT) from both groups (Vu, Vo) are connected to corresponding bit outputs of a two-th higher-order stage (ZTZ) of the clock counter (ZT) .