DE2710270B2 - Circuit arrangement for generating clock pulses synchronized with incoming data pulses - Google Patents

Description

The invention relates to a circuit arrangement of data pulses that are synchronized with incoming data Clock pulses with a frequency controlled by pre-clock pulses with a higher frequency than that of the data pulses Counter.

A known such circuit arrangement according to wi DE-OS 24 62 087 for processing NRZ-L signals has a pulse generator for the pre-clock signals and a three-stage counter fed by this. The third count level of this counter is through the Pulse generator blocked in such a way that a pulse sequence pending at a b5 counting stage after the corresponding Pulse shaping (edge differentiation) results in clock pulses.

The known circuit arrangement is only suitable for the aforementioned NRZ-L signals that are already from a logical combination of a clock pulse sequence with the actual information signal. Since with this signal coding there is already a sequence of impressed clock pulses if no a Signal pulses are transmitted, a synchronization of the resulting clock pulses is without major Effort possible.

From DE-OS 25 35 424 is a further circuit arrangement known for the extraction of clock pulses developed for the processing of MFM signals became. In this case, one oscillator generating the pre-clock signals is replaced by two oscillators obtained from the input data The frequency of the signals is controlled in such a way that it increases or decreases depending on the content of the input data. is reduced. In this way a clock frame for the MFM signals is generated; there also with this one Type of signals transmitted between two consecutive empty bit lengths or bit cells clock pulses in this case, too, the generated clock pulses can easily be checked.

In none of these known circuit arrangements there is a possibility of pulse trains that do not Include clock information to generate a clock signal. But it exists, for example, on the receiving side of telephone transmission lines the need to record the incoming data pulses by inserting them into convert a clock register from serial data into a sequence of parallel data units, for example, to transfer the data to the individual lines going out from the node, for example in the case of time division multiplexing to distribute.

The invention is therefore based on the object of creating a circuit arrangement that includes the incoming Data pulses can generate synchronized clock pulses when the incoming data pulse train does not contain any clock pulses. The circuit arrangement should be universal for different pulse codings be applicable and a simple adaptation of the clock pulses to data trains with different frequencies allow.

The object is achieved with a circuit arrangement of the type mentioned above with the Characteristic of claim 1. Such a circuit arrangement therefore does not require precise synchronization the frequency of the pre-clocks. It only has to be guaranteed that the counter will work during the bit length of the incoming data pulses go through a counting cycle. The pre-clock frequency is adjusted by the check, which occurs once during each bit length, and which otherwise remains static Counter. The incoming data are only used to readjust the circuit according to the invention further counter is required and otherwise forwarded unchanged. The circuit arrangement according to the invention emits synchronized clock pulses even if no information pulse is received for several bit lengths. The review and, if necessary, readjustment the counting content of the second counter influencing the data pulse output is provided by an advantageous Further development of the circuit arrangement according to the invention according to the characteristics of claim 2 designed to be particularly effective and simple, with an advantageous development based on the characteristics of the Claim 3 a sufficiently safe readjustment and review with economical production of the Circuit arrangement with commercially available components

enables

If the phase of the incoming data bits deviates by more than vie of a cycle with respect to the Counting in the first counter, the count in the second counter is increased or decreased by 1 and the position of the Synchronization pulse changes by '/ i6 of a run length of the first counter. This will make the additional advantage achieved that when a noise spike occurs between the incoming data pulses at the output of the synchronizing element, the count of the second counter compared to the count of the first Counter only deviates by one step up or down, so that in this case too the phase of the Synchronization pulse only for '/ ie of a cycle of the first counter is changed.

The invention is explained in more detail below, for example with reference to the drawing; in the drawing shows

F i g. 1 shows a block diagram of a circuit arrangement for generating synchronized clock pulses and

Fig.2a-e graphs of the various Place the circuit arrangement according to FIG. 1 generated pulse trains.

The in F i g. 1 circuit arrangement shown has an input 1, at the pre-clock pulses with a Frequency that is 16 times the frequency of the am Port 2 is incoming serial data. The i ι F i g. 2a pre-clock pulses shown are on a Counter 3 on. Type No. 741 61 from Texas Instruments, for example, can be used for this counter. In the counter 3, a cyclic staircase wave function is created from 16 steps synchronized with the pre-clock pulses (see Fig. 2b). The counter 3 is connected to a read-only memory 4 via a 4-bit multiple address line, which can be, for example, an IC No. 3601-1 from Monolithic Memories Inc. Another counter 5, for example Type 741 93 from Texas Instruments, is also provided with a 4-bit address trunk connected to read-only memory 4; the counters 3 and 5 and the read-only memory 4 are designed so that the Read-only memory as a comparator for the counts of the Counters 3 and 5 are used. In the following, counter 3 is used as the "first counter", counter 5 as the "further counter" designated.

The read-only memory 4 has two outputs 6 and 7; the output 6 carries a signal when the The count of the first counter 3 is greater than that of the further counter 5, while the terminal 7 carries a signal, if the count of the further counter 5 is greater than that of the first counter 3. The outputs 6 and 7 are connected to inputs of AND gates 8 and 9, respectively. These AND gates can, for example Type No. 740 0 from Texas Instruments. The pre-clock pulses are applied simultaneously to a synchronizing element 10, which also receives the incoming serial data pulses from connection 2 Das Synchronizing element 10 gives a synchronized with the pre-clock pulses each time a data pulse arrives Pulse to a further input of the AND gates 8 and 9. The output signal of the AND gate 8 is connected to an up-counting input of the further counter 5, while the output signal of the AND element 9 is applied to a downward counter input of the other counter 5. The read-only memory 4

ίο has another output 11 at which the required clock pulses synchronized with the incoming data pulses are emitted. Of the Read-only memory 4 is programmed in such a way that the synchronized pulses appear at connection 11, when the count of the first counter 3 exceeds the count of the further counter 5 by 8 pulse steps

This circuit arrangement is operated in the following way: The first incoming data bit is effected a first output pulse of the synchronizing member 10 (Fig.2d), it is assumed that this Time the count of the first counter 3 the value 5 (F i g. 2b) and the count of the further counter 5 den Has value 7 (Fig.2c) Since the count of the first counter 3 is smaller than that of the further counter 5,

2 ^r i, the read-only memory generates an output signal at the connection 7; the AND element 9 is therefore activated, since a pulse is emitted by the synchronizing element 10 at the same time. The further counter 5 is therefore brought to a static count of 6 As the

ω read-only memory is programmed so that an output signal is generated at terminal 11 when the count of the first counter 3 is equal to the count of the Another counter is 5 plus the value 8, a clock synchronization pulse (F i g. 2e) is synchronized with

j ") the value 14 of the step function of the first counter 3 (Fig. 2b) at connection 11 of the read-only memory 4 is generated. With the next incoming data bit, the Synchronizing element 10 in turn sends a pulse to the connections of the two AND elements 8 and 9. and the

4 (i first counter 3 at this point in time again has a Count from value 5 up. The static count of the further counter 5 still has a larger one Value than the current value of the count of the first counter 3 and it is again an output

Y-. gnal is generated at the connection 7 of the read-only memory 4, the AND element is activated and the count of the further counter 5 is reduced by one step to the value 5. Another synchronization pulse occurs at terminal 11 when the count

-> o of the first counter 3 has the value 13, i.e. H. the Counting of the further counter 5 with the value 5 plus 8. At the next incoming pulse, i. H. home third Pulse according to Figure 2d, the counts of the two counters 3 and 5 are the same, so that the counter 5 is no longer

ν-, is converted.

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. Circuit arrangement for generating clock pulses synchronized with incoming data pulses with one controlled by pre-clock pulses with a higher frequency than that of the data pulses first counter, characterized in that that a read-only memory (4) is provided, which counts the first counter (3) with the another counter (5) compares and emits a clock pulse each time the count of the first counter (3) is equal to the count of the further counter (5) plus a predetermined one Counting whole numbers of the first counter (3), the first counter (3) during the bit length of the incoming data pulses runs through a counting cycle and the counting of the further counter (S) up to once per bit length checking by the read-only memory (4) remains static 2. Circuit arrangement according to claim 1, characterized in that a synchronizing member (10) it is provided that receives the incoming data pulses and with the also applied Synchronized pre-clock pulses and its output with a first input of two AND gates (8,9) is connected that the second input of the first AND gate (8) with an output (6) of the Read-only memory (4) is connected to which a signal occurs when the count of the first counter (3) is greater than that of the further counter (5) that the output of the first AND gate (8) with the Up counter input of the further counter (5) is connected to the second input of the second AND gate (9) is connected to a further output (7) of the read-only memory (4) to which a Signal occurs when the count of the first counter (3) is less than that of the further counter (5) and that the output of the second AND element (9) with the downward counter input of the further counter (5) connected is. 3. Circuit arrangement according to one of claims 1 or 2, characterized in that the first Counter (3) with a step waveform (Fig.2a) before the cycle return 16 pulse steps generated and that at an output (11) of the read-only memory (4) clock pulses (F i g. 2e) are emitted, if the count of the first counter (3) is equal to the count of the second counter (5) plus 8 pulse steps of the first counter (3).