DE3483927D1 - Geraet zur systemtaktunterbrechung bei einem anfangsfehlereintritt. - Google Patents
Geraet zur systemtaktunterbrechung bei einem anfangsfehlereintritt.Info
- Publication number
- DE3483927D1 DE3483927D1 DE8484106838T DE3483927T DE3483927D1 DE 3483927 D1 DE3483927 D1 DE 3483927D1 DE 8484106838 T DE8484106838 T DE 8484106838T DE 3483927 T DE3483927 T DE 3483927T DE 3483927 D1 DE3483927 D1 DE 3483927D1
- Authority
- DE
- Germany
- Prior art keywords
- interrupting
- system clock
- initial error
- error entry
- entry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/509,494 US4616335A (en) | 1983-06-30 | 1983-06-30 | Apparatus for suspending a system clock when an initial error occurs |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3483927D1 true DE3483927D1 (de) | 1991-02-21 |
Family
ID=24026834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484106838T Expired - Fee Related DE3483927D1 (de) | 1983-06-30 | 1984-06-15 | Geraet zur systemtaktunterbrechung bei einem anfangsfehlereintritt. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4616335A (de) |
EP (1) | EP0130432B1 (de) |
JP (1) | JPS6010345A (de) |
CA (1) | CA1208800A (de) |
DE (1) | DE3483927D1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0256267B1 (de) * | 1986-08-12 | 1994-03-02 | Hitachi, Ltd. | Mikroprozessor zur Datentransferwiederholung |
US4916697A (en) * | 1988-06-24 | 1990-04-10 | International Business Machines Corporation | Apparatus for partitioned clock stopping in response to classified processor errors |
JPH0439707A (ja) * | 1990-06-06 | 1992-02-10 | Mitsubishi Electric Corp | 数値制御装置の非常停止装置 |
US6343363B1 (en) * | 1994-09-22 | 2002-01-29 | National Semiconductor Corporation | Method of invoking a low power mode in a computer system using a halt instruction |
JP2006259869A (ja) * | 2005-03-15 | 2006-09-28 | Fujitsu Ltd | マルチプロセッサシステム |
GB2456618A (en) * | 2008-01-15 | 2009-07-22 | Ibm | Delaying the stop-clock signal of a chip by a set amount of time so that error handling and recovery can be performed before the clock is stopped |
US8042010B2 (en) * | 2008-10-22 | 2011-10-18 | Synopsys, Inc. | Two-phase clock-stalling technique for error detection and error correction |
US8583962B2 (en) | 2009-11-11 | 2013-11-12 | International Business Machines Corporation | Method, device, computer program product and data processing program for handling communication link problems between a first communication means and a second communication means |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3229251A (en) * | 1962-03-26 | 1966-01-11 | Ibm | Computer error stop system |
US3245048A (en) * | 1963-12-23 | 1966-04-05 | Ibm | Computer clock phase lock |
US3810120A (en) * | 1971-02-12 | 1974-05-07 | Honeywell Inf Systems | Automatic deactivation device |
JPS5236665B2 (de) * | 1972-12-21 | 1977-09-17 | ||
US4072852A (en) * | 1976-08-23 | 1978-02-07 | Honeywell Inc. | Digital computer monitoring and restart circuit |
JPS5642825A (en) * | 1979-09-14 | 1981-04-21 | Clarion Co Ltd | Compensating circuit for data reading clock |
US4348722A (en) * | 1980-04-03 | 1982-09-07 | Motorola, Inc. | Bus error recognition for microprogrammed data processor |
US4463440A (en) * | 1980-04-15 | 1984-07-31 | Sharp Kabushiki Kaisha | System clock generator in integrated circuit |
JPS5755456A (en) * | 1980-09-19 | 1982-04-02 | Hitachi Ltd | Career recording system |
DE3047239C2 (de) * | 1980-12-16 | 1982-12-30 | Wandel & Goltermann Gmbh & Co, 7412 Eningen | Verfahren und Schaltungsanordnung zum Messen der Güte digitaler Übertragungsstrecken und -einrichtungen |
US4392226A (en) * | 1981-09-28 | 1983-07-05 | Ncr Corporation | Multiple source clock encoded communications error detection circuit |
US4453215A (en) * | 1981-10-01 | 1984-06-05 | Stratus Computer, Inc. | Central processing apparatus for fault-tolerant computing |
US4464751A (en) * | 1981-11-10 | 1984-08-07 | International Business Machines Corp. | Machine check coordination |
US4539682A (en) * | 1983-04-11 | 1985-09-03 | The United States Of America As Represented By The Secretary Of The Army | Method and apparatus for signaling on-line failure detection |
-
1983
- 1983-06-30 US US06/509,494 patent/US4616335A/en not_active Expired - Fee Related
-
1984
- 1984-03-16 JP JP59049452A patent/JPS6010345A/ja active Granted
- 1984-05-18 CA CA000454741A patent/CA1208800A/en not_active Expired
- 1984-06-15 EP EP84106838A patent/EP0130432B1/de not_active Expired
- 1984-06-15 DE DE8484106838T patent/DE3483927D1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS6010345A (ja) | 1985-01-19 |
CA1208800A (en) | 1986-07-29 |
US4616335A (en) | 1986-10-07 |
EP0130432A2 (de) | 1985-01-09 |
EP0130432A3 (en) | 1987-10-14 |
JPH0326861B2 (de) | 1991-04-12 |
EP0130432B1 (de) | 1991-01-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |