DE3476499D1 - Latching circuit array of logic gates - Google Patents

Latching circuit array of logic gates

Info

Publication number
DE3476499D1
DE3476499D1 DE8484104078T DE3476499T DE3476499D1 DE 3476499 D1 DE3476499 D1 DE 3476499D1 DE 8484104078 T DE8484104078 T DE 8484104078T DE 3476499 T DE3476499 T DE 3476499T DE 3476499 D1 DE3476499 D1 DE 3476499D1
Authority
DE
Germany
Prior art keywords
logic gates
latching circuit
circuit array
array
latching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484104078T
Other languages
English (en)
Inventor
Gerald Adrian Maley
Douglas Wayne Westcott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3476499D1 publication Critical patent/DE3476499D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
DE8484104078T 1983-06-30 1984-04-12 Latching circuit array of logic gates Expired DE3476499D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/509,273 US4564772A (en) 1983-06-30 1983-06-30 Latching circuit speed-up technique

Publications (1)

Publication Number Publication Date
DE3476499D1 true DE3476499D1 (en) 1989-03-02

Family

ID=24025949

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484104078T Expired DE3476499D1 (en) 1983-06-30 1984-04-12 Latching circuit array of logic gates

Country Status (4)

Country Link
US (1) US4564772A (de)
EP (1) EP0130293B1 (de)
JP (1) JPH0614609B2 (de)
DE (1) DE3476499D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4940908A (en) * 1989-04-27 1990-07-10 Advanced Micro Devices, Inc. Method and apparatus for reducing critical speed path delays
JPH03112651A (ja) * 1989-09-27 1991-05-14 Meisho Kk 化粧板の製造方法
US5467311A (en) * 1990-07-31 1995-11-14 International Business Machines Corporation Circuit for increasing data-valid time which incorporates a parallel latch
US6658551B1 (en) * 2000-03-30 2003-12-02 Agere Systems Inc. Method and apparatus for identifying splittable packets in a multithreaded VLIW processor
US7245150B2 (en) * 2005-12-15 2007-07-17 P.A. Semi, Inc. Combined multiplex or/flop
US7319344B2 (en) * 2005-12-15 2008-01-15 P.A. Semi, Inc. Pulsed flop with embedded logic
US7373569B2 (en) * 2005-12-15 2008-05-13 P.A. Semi, Inc. Pulsed flop with scan circuitry
CN112383303B (zh) * 2020-12-04 2023-08-29 北京时代民芯科技有限公司 一种动态逻辑结构的鉴频鉴相器

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2942192A (en) * 1956-10-11 1960-06-21 Bell Telephone Labor Inc High speed digital data processing circuits
US3154744A (en) * 1959-12-09 1964-10-27 Ibm Double trigger composed of binary logic elements
US3467839A (en) * 1966-05-18 1969-09-16 Motorola Inc J-k flip-flop
US3530384A (en) * 1968-07-29 1970-09-22 Us Navy Plural-input dropout and noise detection circuit for magnetic recording tape
US3679915A (en) * 1971-03-04 1972-07-25 Ibm Polarity hold latch with common data input-output terminal
DE2137068C3 (de) * 1971-07-24 1981-01-29 Fried. Krupp Gmbh, 4300 Essen Schaltanordnung zum Unterdrücken von Störimpulsen
US3723760A (en) * 1971-11-29 1973-03-27 Bell Canada Northern Electric Transmission gating circuit
US3740590A (en) * 1971-12-17 1973-06-19 Ibm Latch circuit
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
US3882325A (en) * 1973-12-10 1975-05-06 Ibm Multi-chip latching circuit for avoiding input-output pin limitations
GB1543716A (en) * 1975-03-11 1979-04-04 Plessey Co Ltd Injection logic arrangements
US4019144A (en) * 1975-09-12 1977-04-19 Control Data Corporation Conditional latch circuit
US4085341A (en) * 1976-12-20 1978-04-18 Motorola, Inc. Integrated injection logic circuit having reduced delay
US4078204A (en) * 1977-01-31 1978-03-07 Gte Automatic Electric (Canada) Limited Di-phase pulse receiving system
JPS5449039A (en) * 1977-09-27 1979-04-18 Mitsubishi Electric Corp Logic circuit
US4315167A (en) * 1979-09-10 1982-02-09 International Business Machines Corporation Self-switching bidirectional digital line driver
US4314166A (en) * 1980-02-22 1982-02-02 Rca Corporation Fast level shift circuits
US4439690A (en) * 1982-04-26 1984-03-27 International Business Machines Corporation Three-gate hazard-free polarity hold latch

Also Published As

Publication number Publication date
EP0130293A2 (de) 1985-01-09
JPH0614609B2 (ja) 1994-02-23
EP0130293B1 (de) 1989-01-25
EP0130293A3 (en) 1987-03-04
JPS6010910A (ja) 1985-01-21
US4564772A (en) 1986-01-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee